参数资料
型号: IS61VPS51218A-250B3
厂商: INTEGRATED SILICON SOLUTION INC
元件分类: SRAM
英文描述: 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
中文描述: 512K X 18 CACHE SRAM, 2.6 ns, PBGA165
封装: 13 X 15 MM, 1 MM PITCH, PLASTIC, BGA-165
文件页数: 3/35页
文件大小: 562K
代理商: IS61VPS51218A-250B3
Integrated Silicon Solution, Inc.
11
Rev. I
01/13/09
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
PARTIAL TRUTH TABLE
Function
GW
BWE
BWa
BWb
BWc
BWd
Read
H
X
Read
H
L
H
WriteByte1
H
L
H
WriteAllBytes
H
L
WriteAllBytes
L
X
TRUTH TABLE(1-8)
OPERATION
ADDRESS CE CE2
CE2 ZZ ADSP ADSC ADV
WRITE OE
CLK
DQ
DeselectCycle,Power-Down
None
H
X
L
X
L
X
L-H
High-Z
DeselectCycle,Power-Down
None
L
X
L
X
L-H
High-Z
DeselectCycle,Power-Down
None
L
H
X
L
X
L-H
High-Z
DeselectCycle,Power-Down
None
L
X
L
H
L
X
L-H
High-Z
DeselectCycle,Power-Down
None
L
H
X
L
H
L
X
L-H
High-Z
SnoozeMode,Power-Down
None
X
H
X
High-Z
ReadCycle,BeginBurst
External
L
H
L
X
L
L-H
Q
ReadCycle,BeginBurst
External
L
H
L
X
H
L-H
High-Z
WriteCycle,BeginBurst
External
L
H
L
H
L
X
L
X
L-H
D
ReadCycle,BeginBurst
External
L
H
L
H
L
X
H
L
L-H
Q
ReadCycle,BeginBurst
External
L
H
L
H
L
X
H
L-H
High-Z
ReadCycle,ContinueBurst
Next
X
L
H
L
H
L
L-H
Q
ReadCycle,ContinueBurst
Next
X
L
H
L
H
L-H
High-Z
ReadCycle,ContinueBurst
Next
H
X
L
X
H
L
H
L
L-H
Q
ReadCycle,ContinueBurst
Next
H
X
L
X
H
L
H
L-H
High-Z
WriteCycle,ContinueBurst
Next
X
L
H
L
X
L-H
D
WriteCycle,ContinueBurst
Next
H
X
L
X
H
L
X
L-H
D
ReadCycle,SuspendBurst
Current
X
L
H
L
L-H
Q
ReadCycle,SuspendBurst
Current
X
L
H
L-H
High-Z
ReadCycle,SuspendBurst
Current
H
X
L
X
H
L
L-H
Q
ReadCycle,SuspendBurst
Current
H
X
L
X
H
L-H
High-Z
WriteCycle,SuspendBurst
Current
X
L
H
L
X
L-H
D
WriteCycle,SuspendBurst
Current
H
X
L
X
H
L
X
L-H
D
NOTE:
1. Xmeans“Don’tCare.”HmeanslogicHIGH.LmeanslogicLOW.
2. ForWRITE, L means one or more byte write enable signals (BWa-d) and BWEareLOWorGWisLOW.WRITE=Hforall
BWx
, BWE, GWHIGH.
3. BWaenablesWRITEstoDQa’sandDQPa.BWbenablesWRITEstoDQb’sandDQPb.BWcenablesWRITEstoDQc’s and
DQPc.BWdenablesWRITEstoDQd’sandDQPd.DQPaandDQPbareavailableonthex18version. DQPa-DQPdareavail-
ableonthex36version.
4. AllinputsexceptOEandZZmustmeetsetupandholdtimesaroundtherisingedge(LOWtoHIGH)ofCLK.
5. Waitstatesareinsertedbysuspendingburst.
6. ForaWRITEoperationfollowingaREADoperation,OEmustbeHIGHbeforetheinputdatasetuptimeandheldHIGHduring
the input data hold time.
7. ThisdevicecontainscircuitrythatwillensuretheoutputswillbeinHigh-Zduringpower-up.
8. ADSPLOWalwaysinitiatesaninternalREADattheL-HedgeofCLK.AWRITEisperformedbysettingoneormorebytewrite
enable signals and BWELOWorGWLOWforthesubsequentL-HedgeofCLK.SeeWRITEtimingdiagramforclarification.
相关PDF资料
PDF描述
IS61VPS51218A-250B3I 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
IS61VPS51218A-250TQ 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
IS61VPS51218A-250TQI 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
IS61VPS51236A-200B2 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
IS62WV10248DBLL-45MLI 1M X 8 STANDARD SRAM, 45 ns, PBGA48
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