参数资料
型号: ISP1160BD/01,118
厂商: ST-ERICSSON
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封装: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件页数: 39/88页
文件大小: 394K
代理商: ISP1160BD/01,118
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 05 — 24 December 2004
44 of 88
9397 750 13963
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
10.2 HC frame counter registers
10.2.1
HcFmInterval register (R/W: 0DH/8DH)
The HcFmInterval register contains a 14-bit value which indicates the bit time interval
in a frame (that is, between two consecutive SOFs), and a 15-bit value indicating the
full-speed maximum packet size that the HC may transmit or receive without causing
a scheduling overrun. The HCD may carry out minor adjustments on the
FrameInterval by writing a new value at each SOF. This allows the HC to synchronize
with an external clock resource and to adjust any unknown clock offset.
Code (Hex): 0D — read
Code (Hex): 8D — write
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
RHSC
FNO
UE
RD
SF
reserved
SO
Reset
00000000
Access
R/W
Table 19:
HcInterruptDisable register: bit description
Bit
Symbol
Description
31
MIE
A logic 0 is ignored by the HC. A logic 1 disables interrupt
generation due to events specied in other bits of this register. This
eld is set after a hardware or software reset.
30 to 7
-
reserved
6
RHSC
0 — ignore
1 — disable interrupt generation due to Root Hub Status Change
5
FNO
0 — ignore
1 — disable interrupt generation due to Frame Number Overow
4UE
0 — ignore
1 — disable interrupt generation due to Unrecoverable Error
3RD
0 — ignore
1 — disable interrupt generation due to Resume Detect
2SF
0 — ignore
1 — disable interrupt generation due to Start of Frame
1
-
reserved
0SO
0 — ignore
1 — disable interrupt generation due to Scheduling Overrun
Table 20:
HcFmInterval register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
FIT
FSMPS[14:8]
Reset
00000000
Access
R/W
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