参数资料
型号: ISP1160BD/01,118
厂商: ST-ERICSSON
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封装: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件页数: 45/88页
文件大小: 394K
代理商: ISP1160BD/01,118
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 05 — 24 December 2004
5 of 88
9397 750 13963
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
D4
4
I/O
bit 4 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D5
5
I/O
bit 5 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D6
6
I/O
bit 6 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D7
7
I/O
bit 7 of bidirectional data; slew-rate controlled; TTL input;
three-state output
DGND
8
-
digital ground
D8
9
I/O
bit 8 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D9
10
I/O
bit 9 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D10
11
I/O
bit 10 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D11
12
I/O
bit 11 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D12
13
I/O
bit 12 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D13
14
I/O
bit 13 of bidirectional data; slew-rate controlled; TTL input;
three-state output
DGND
15
-
digital ground
D14
16
I/O
bit 14 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D15
17
I/O
bit 15 of bidirectional data; slew-rate controlled; TTL input;
three-state output
DGND
18
-
digital ground
VHOLD1
19
-
voltage holding pin 1; internally connected to the VREG(3V3)
and VHOLD2 pins. When VCC is connected to 5 V, this pin
will output 3.3 V, hence do not connect it to 5 V. When VCC
is connected to 3.3 V, this pin can either be connected to
3.3 V or left unconnected. In all cases, decouple this pin to
DGND.
n.c.
20
-
no connection; leave this pin open
CS_N
21
I
chip select input
RD_N
22
I
read strobe input
WR_N
23
I
write strobe input
VHOLD2
24
-
voltage holding pin 2; internally connected to the VREG(3V3)
and VHOLD1 pins. When VCC is connected to 5 V, this pin
will output 3.3 V, hence do not connect it to 5 V. When VCC
is connected to 3.3 V, this pin can either be connected to
3.3 V or left unconnected. In all cases, decouple this pin to
DGND.
DREQ
25
O
HC DMA request output (programmable polarity); signals
to the DMA controller that the ISP1160 wants to start a
DMA transfer; see Section 10.4.1
Table 2:
Pin description LQFP64…continued
Symbol[1]
Pin
Type
Description
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