参数资料
型号: ISP1160BD/01,118
厂商: ST-ERICSSON
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封装: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件页数: 53/88页
文件大小: 394K
代理商: ISP1160BD/01,118
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 05 — 24 December 2004
57 of 88
9397 750 13963
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
10.4 HC DMA and interrupt control registers
10.4.1
HcHardwareConguration register (R/W: 20H/A0H)
Code (Hex): 20 — read
Code (Hex): A0 — write
Table 36:
HcHardwareConguration register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
2_Down
stream
Port15K
resistorsel
Suspend
ClkNotStop
AnalogOC
Enable
reserved
DACKMode
Reset
00000
00
0
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
EOTInput
Polarity
DACKInput
Polarity
DREQ
Output
Polarity
DataBusWidth[1:0]
Interrupt
Output
Polarity
Interrupt
PinTrigger
InterruptPin
Enable
Reset
00101
00
0
Access
R/W
Table 37:
HcHardwareConguration register: bit description
Bit
Symbol
Description
15 to 13 -
reserved
12
2_DownstreamPort15K
resistorsel
0 — use external 15 k
resistors for downstream ports
1 — use built-in resistors for downstream ports
11
SuspendClkNotStop
0 — clock can be stopped
1 — clock can not be stopped
10
AnalogOCEnable
0 — use external OC detection; digital input
1 — use on-chip OC detection; analog input
9
-
reserved
8
DACKMode
0 — normal operation; pin DACK_N is used with read and
write signals
1 — reserved
7
EOTInputPolarity
0 — active LOW
1 — active HIGH
6
DACKInputPolarity
0 — active LOW
1 — reserved
5
DREQOutputPolarity
0 — active LOW
1 — active HIGH
4 to 3
DataBusWidth[1:0]
These bits are xed at logic 0 and logic 1 for the ISP1160.
01 — 16 bits
Others — reserved
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