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参数资料
型号： ISP1160BD/01,118
厂商： ST-ERICSSON
元件分类： 总线控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封装： 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件页数： 55/88页
文件大小： 394K
代理商： ISP1160BD/01,118
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 05 — 24 December 2004
59 of 88
9397 750 13963
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
10.4.3
HcTransferCounter register (R/W: 22H/A2H)
This register holds the number of bytes of a PIO or DMA transfer. For a PIO transfer,
the number of bytes being read or written to the Isochronous Transfer List (ITL) or
Acknowledged Transfer List (ATL) buffer RAM must be written into this register. For a
DMA transfer, the number of bytes must be written into this register as well. However,
for this counter to be read into the DMA counter, the HCD must set bit 2
(DMACounterSelect) of the HcDMAConguration register. The counter value for ATL
must not be greater than 1000H, and for ITL it must not be greater than 800H. When
the byte count of the data transfer reaches this value, the HC will generate an internal
EOT signal to set bit 2 (AllEOTInterrupt) of the Hc
PInterrupt register, and also
update the HcBufferStatus register.
Code (Hex): 22 — read
Code (Hex): A2 — write
10.4.4
Hc
PInterrupt register (R/W: 24H/A4H)
All the bits in this register will be active on power-on reset. However, none of the
active bits will cause an interrupt on the interrupt pin (INT) unless they are set by the
respective bits in the Hc
PInterruptEnable register, and together with bit 0 of the
HcHardwareConguration register.
2
DMACounter
Select
0 — DMA counter not used. External EOT must be used
1 — enables the DMA counter for DMA transfer.
HcTransferCounter register must be lled with non-zero values for
DREQ to be raised after bit DMA Enable is set.
1
ITL_ATL_
DataSelect
0 — ITL buffer RAM selected for ITL data
1 — ATL buffer RAM selected for ATL data
0
DMARead
WriteSelect
0 — read from the HC FIFO buffer RAM
1 — write to the HC FIFO buffer RAM
Table 39:
HcDMAConguration register: bit description…continued
Bit
Symbol
Description
Table 40:
HcTransferCounter register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
Counter value
Reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
Counter value
Reset
00000000
Access
R/W
Table 41:
HcTransferCounter register: bit description
Bit
Symbol
Description
15 to 0
Counter
value
The number of data bytes to be read to or written from RAM.
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