参数资料
型号: ISP1160BD/01,118
厂商: ST-ERICSSON
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封装: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件页数: 46/88页
文件大小: 394K
代理商: ISP1160BD/01,118
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 05 — 24 December 2004
50 of 88
9397 750 13963
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
10.3.2
HcRhDescriptorB register (R/W: 13H/93H)
The HcRhDescriptorB register is the second register of two describing the
characteristics of the Root Hub. These elds are written during initialization to
correspond with the system implementation. Reset values are
implementation-specic (IS).
Code (Hex): 13 — read
Code (Hex): 93 — write
9
NPS
NoPowerSwitching: This bit is used to specify whether power
switching is supported or ports are always powered. When this bit
is cleared, bit PowerSwitchingMode species global or per-port
switching.
0 — ports are power switched
1 — ports are always powered on when the HC is powered on
8
PSM
PowerSwitchingMode: This bit is used to specify how the power
switching of the Root Hub ports is controlled. This eld is valid only
if the NoPowerSwitching eld is cleared.
0 — all ports are powered at the same time
1 — each port is powered individually. This mode allows port
power to be controlled by either the global switch or per-port
switching. If bit PortPowerControlMask is set, the port responds to
only port power commands (Set/ClearPortPower). If the port mask
is cleared, then the port is controlled only by the global power
switch (Set/ClearGlobalPower).
7 to 2
-
reserved
1 to 0
NDP[1:0]
NumberDownstreamPorts: These bits specify the number of
downstream ports supported by the Root Hub. The maximum
number of ports supported by the ISP1160 is 2.
Table 29:
HcRhDescriptorA register: bit description…continued
Bit
Symbol
Description
Table 30:
HcRhDescriptorB register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
reserved
Reset
N/A
Access
RRRRRRRR
Bit
23
22
21
20
19
18
17
16
Symbol
reserved
PPCM[2:0]
Reset
N/A
IS
Access
RRRRR
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
Reset
N/A
Access
RRRRRRRR
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