参数资料
型号: ISP1160BD/01,118
厂商: ST-ERICSSON
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封装: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件页数: 78/88页
文件大小: 394K
代理商: ISP1160BD/01,118
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 05 — 24 December 2004
8 of 88
9397 750 13963
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
7.
Functional description
7.1 PLL clock multiplier
A 6 MHz to 48 MHz clock multiplier Phase-Locked Loop (PLL) is integrated on-chip.
This allows for the use of a low-cost 6 MHz crystal, which also minimizes EMI. No
external components are required for the operation of the PLL.
7.2 Bit clock recovery
The bit clock recovery circuit recovers the clock from the incoming USB data stream
by using a 4 times oversampling principle. It is able to track jitter and frequency drift
as specied in
Universal Serial Bus Specication Rev. 2.0.
7.3 Analog transceivers
Two sets of transceivers are embedded in the chip for downstream ports with USB
connector type A. The integrated transceivers are compliant with the
Universal Serial
Bus Specication Rev. 2.0. These transceivers interface directly with the USB
connectors and cables through external termination resistors.
7.4 Philips Serial Interface Engine (SIE)
The Philips SIE implements the full USB protocol layer. It is completely hardwired for
speed and needs no rmware intervention. The functions of this block include:
synchronization pattern recognition, parallel to serial conversion, bit (de)stufng,
CRC checking and generation, Packet IDentier (PID) verication and generation,
address recognition, and handshake evaluation and generation.
8.
Microprocessor bus interface
8.1 Programmed I/O (PIO) addressing mode
A generic PIO interface is dened for speed and ease-of-use. It also allows direct
interfacing to most microcontrollers. To a microcontroller, the ISP1160 appears as a
memory device with a 16-bit data bus and uses the A0 address line to access internal
control registers and FIFO buffer RAM. Therefore, the ISP1160 occupies only two
I/O ports or two memory locations of a microprocessor. External microprocessors can
read from or write to the ISP1160’s internal control registers and FIFO buffer RAM
through the Programmed I/O (PIO) operating mode. Figure 3 shows the
Programmed I/O interface between a microprocessor and the ISP1160.
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