参数资料
型号: ISP1181ABS,551
厂商: ST-ERICSSON
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC48
封装: 7 X 7 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-619-2, HVQFN-48
文件页数: 18/70页
文件大小: 341K
代理商: ISP1181ABS,551
Philips Semiconductors
ISP1181A
Full-speed USB peripheral controller
Product data
Rev. 05 — 08 December 2004
25 of 70
9397 750 13959
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
[1]
With N representing the number of bytes, the number of words for 16-bit bus width is: (N + 1) DIV 2.
[2]
When accessing an 8-bit register in 16-bit mode, the upper byte is invalid.
[3]
In 8-bit bus mode this command requires more time to complete than other commands. See Table 58.
[4]
During isochronous transfer in 16-bit mode, because N
≤ 1023, the rmware must take care of the upper byte.
[5]
Validating an OUT endpoint buffer causes unpredictable behavior of ISP1181A.
[6]
Clearing an IN endpoint buffer causes unpredictable behavior of ISP1181A.
[7]
Reads a copy of the Status Register: executing this command does not clear any status bits or interrupt bits.
12.1 Initialization commands
Initialization commands are used during the enumeration process of the USB
network. These commands are used to congure and enable the embedded
endpoints. They also serve to set the USB assigned address of ISP1181A and to
perform a device reset.
12.1.1
Write/Read Endpoint Conguration
This command is used to access the Endpoint Conguration Register (ECR) of the
target endpoint. It denes the endpoint type (isochronous or bulk/interrupt), direction
(OUT/IN), FIFO size and buffering scheme. It also enables the endpoint FIFO. The
register bit allocation is shown in Table 14. A bus reset will disable all endpoints.
The allocation of FIFO memory only takes place after all 16 endpoints have been
congured in sequence (from endpoint 0 OUT to endpoint 14). Although the control
endpoints have xed congurations, they must be included in the initialization
sequence and be congured with their default values (see Table 4). Automatic FIFO
allocation starts when endpoint 14 has been congured.
Unstall Endpoint n
(n = 1 to 14)
Endpoint 1 to 14
82 to 8F
-
Check Control OUT Status[7]
Endpoint Status Image Register
endpoint 0 OUT
D0
read 1 byte[2]
Check Control IN Status[7]
Endpoint Status Image Register
endpoint 0 IN
D1
read 1 byte[2]
Check Endpoint n Status
(n = 1 to 14)[7]
Endpoint Status Image Register n
endpoint 1 to 14
D2 to DF
read 1 byte[2]
Acknowledge Setup
Endpoint 0 IN and OUT
F4
General commands
Read Control OUT Error Code
Error Code Register
endpoint 0 OUT
A0
read 1 byte[2]
Read Control IN Error Code
Error Code Register
endpoint 0 IN
A1
read 1 byte[2]
Read Endpoint n Error Code
(n = 1 to 14)
Error Code Register
endpoint 1 to 14
A2 to AF
read 1 byte[2]
Unlock Device
all registers with write access
B0
write 2 bytes
Write/Read Scratch Register
Scratch Register
B2/B3
write/read 2 bytes
Read Frame Number
Frame Number Register
B4
read 1 or 2 bytes
Read Chip ID
Chip ID Register
B5
read 2 bytes
Read Interrupt Register
Interrupt Register
C0
read 4 bytes
Table 13:
Command and register summary…continued
Name
Destination
Code (Hex)
Transaction[1]
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