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| 型号： | ISP1181ABS,551 |
| 厂商： | ST-ERICSSON |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQCC48 |
| 封装： | 7 X 7 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-619-2, HVQFN-48 |
| 文件页数： | 21/70页 |
| 文件大小： | 341K |
| 代理商： | ISP1181ABS,551 |
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Philips Semiconductors
ISP1181A
Full-speed USB peripheral controller
Product data
Rev. 05 — 08 December 2004
28 of 70
9397 750 13959
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
12.1.4
Write/Read Hardware Conguration
This command is used to access the Hardware Conguration Register, which
consists of 2 bytes. The rst (lower) byte contains the device conguration and
control values, the second (upper) byte holds the clock control bits and the clock
division factor. The bit allocation is given in Table 20. A bus reset will not change any
of the programmed bit values.
The Hardware Conguration Register controls the connection to the USB bus, clock
activity and power supply during ‘suspend’ state, output clock frequency, DMA
operating mode and pin congurations (polarity, signalling mode).
Code (Hex): BA/BB — write/read Hardware Conguration Register
Transaction — write/read 2 bytes
Table 20:
Hardware Conguration Register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
EXTPUL
NOLAZY
CLKRUN
CLKDIV[3:0]
Reset
00100011
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
DAKOLY
DRQPOL
DAKPOL
EOTPOL
WKUPCS
PWROFF
INTLVL
INTPOL
Reset
01000000
Access
R/W
Table 21:
Hardware Conguration Register: bit description
Bit
Symbol
Description
15
-
reserved
14
EXTPUL
A logic 1 indicates that an external 1.5 k
pull-up resistor is
used on pin D
+ and that SoftConnect is not used. Bus reset
value: unchanged.
13
NOLAZY
A logic 1 disables output on pin CLKOUT of the LazyClock
frequency (100 kHz
± 50 %) during ‘suspend’ state. A logic 0
causes pin CLKOUT to switch to LazyClock output after
approximately 2 ms delay, following the setting of bit GOSUSP
in the Mode Register. Bus reset value: unchanged.
12
CLKRUN
A logic 1 indicates that the internal clocks are always running,
even during ‘suspend’ state. A logic 0 switches off the internal
oscillator and PLL, when they are not needed. During ‘suspend’
state this bit must be made logic 0 to meet the suspend current
requirements. The clock is stopped after a delay of
approximately 2 ms, following the setting of bit GOSUSP in the
Mode Register. Bus reset value: unchanged.
11 to 8
CLKDIV[3:0]
This eld species the clock division factor N, which controls the
clock frequency on output CLKOUT. The output frequency in
MHz is given by
. The clock frequency range is
3 MHz to 48 MHz (N=0to 15). with a reset value of 12 MHz
(N = 3). The hardware design guarantees no glitches during
frequency change. Bus reset value: unchanged.
7
DAKOLY
A logic 1 selects DACK-only DMA mode. A logic 0 selects 8237
compatible DMA mode. Bus reset value: unchanged.
48
N
1
+
()
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