参数资料
型号: ISP1181ABS,551
厂商: ST-ERICSSON
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC48
封装: 7 X 7 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-619-2, HVQFN-48
文件页数: 19/70页
文件大小: 341K
代理商: ISP1181ABS,551
Philips Semiconductors
ISP1181A
Full-speed USB peripheral controller
Product data
Rev. 05 — 08 December 2004
26 of 70
9397 750 13959
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Remark: If any change is made to an endpoint conguration which affects the
allocated memory (size, enable/disable), the FIFO memory contents of all endpoints
becomes invalid. Therefore, all valid data must be removed from enabled endpoints
before changing the conguration.
Code (Hex): 20 to 2F — write (control OUT, control IN, endpoint 1 to 14)
Code (Hex): 30 to 3F — read (control OUT, control IN, endpoint 1 to 14)
Transaction — write/read 1 byte
12.1.2
Write/Read Device Address
This command is used to set the USB assigned address in the Address Register and
enable the USB device. The Address Register bit allocation is shown in Table 16.
A USB bus reset sets the device address to 00H (internally) and enables the device.
The value of the Address Register (accessible by the micro) is not altered by the bus
reset. In response to the standard USB request Set Address the rmware must issue
a Write Device Address command, followed by sending an empty packet to the host.
The new device address is activated when the host acknowledges the empty packet.
Code (Hex): B6/B7 — write/read Address Register
Transaction — write/read 1 byte
Table 14:
Endpoint Conguration Register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
FIFOEN
EPDIR
DBLBUF
FFOISO
FFOSZ[3:0]
Reset
00000000
Access
R/W
Table 15:
Endpoint Conguration Register: bit description
Bit
Symbol
Description
7
FIFOEN
A logic 1 indicates an enabled FIFO with allocated memory.
A logic 0 indicates a disabled FIFO (no bytes allocated).
6
EPDIR
This bit denes the endpoint direction (0 = OUT, 1 = IN). It also
determines the DMA transfer direction (0 = read, 1 = write).
5
DBLBUF
A logic 1 indicates that this endpoint has double buffering.
4
FFOISO
A logic 1 indicates an isochronous endpoint. A logic 0 indicates
a bulk or interrupt endpoint.
3 to 0
FFOSZ[3:0]
Selects the FIFO size according to Table 5
Table 16:
Address Register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
DEVEN
DEVADR[6:0]
Reset
00000000
Access
R/W
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