参数资料
型号: ISP1181ABS,551
厂商: ST-ERICSSON
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC48
封装: 7 X 7 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-619-2, HVQFN-48
文件页数: 9/70页
文件大小: 341K
代理商: ISP1181ABS,551
Philips Semiconductors
ISP1181A
Full-speed USB peripheral controller
Product data
Rev. 05 — 08 December 2004
17 of 70
9397 750 13959
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
The following example shows the steps which occur in a typical DMA transfer:
1. ISP1181A receives a data packet in one of its endpoint FIFOs; the packet must
be transferred to memory address 1234H.
2. ISP1181A asserts the DREQ signal requesting the 8237 for a DMA transfer.
3. The 8237 asks the CPU to release the bus by asserting the HRQ signal.
4. After completing the current instruction cycle, the CPU places the bus control
signals (MEMR, MEMW, IOR and IOW) and the address lines in three-state and
asserts HLDA to inform the 8237 that it has control of the bus.
5. The 8237 now sets its address lines to 1234H and activates the MEMW and IOR
control signals.
6. The 8237 asserts DACK to inform the ISP1181A that it will start a DMA transfer.
7. The ISP1181A now places the byte or word to be transferred on the data bus
lines, because its RD signal was asserted by the 8237.
8. The 8237 waits one DMA clock period and then de-asserts MEMW and IOR. This
latches and stores the byte or word at the desired memory location. It also
informs the ISP1181A that the data on the bus lines has been transferred.
9. The ISP1181A de-asserts the DREQ signal to indicate to the 8237 that DMA is
no longer needed. In Single cycle mode this is done after each byte or word, in
Burst mode following the last transferred byte or word of the DMA cycle.
10. The 8237 de-asserts the DACK output indicating that the ISP1181A must stop
placing data on the bus.
11. The 8237 places the bus control signals (MEMR, MEMW, IOR and IOW) and the
address lines in three-state and de-asserts the HRQ signal, informing the CPU
that it has released the bus.
12. The CPU acknowledges control of the bus by de-asserting HLDA. After activating
the bus control lines (MEMR, MEMW, IOR and IOW) and the address lines, the
CPU resumes the execution of instructions.
For a typical bulk transfer the above process is repeated 64 times, once for each byte.
After each byte the address register in the DMA controller is incremented and the
byte counter is decremented. When using 16-bit DMA, the number of transfers is 32,
and address incrementing and byte counter decrementing is done by 2 for each word.
10.3 DACK-only mode
The DACK-only DMA mode is selected by setting bit DAKOLY in the Hardware
Conguration Register (see Table 20). The pin functions for this mode are shown in
Table 9. A typical example of ISP1181A in DACK-only DMA mode is given in Figure 5.
Table 9:
DACK-only mode: pin functions
Symbol
Description
I/O
Function
DREQ
DMA request
O
ISP1181A requests a DMA transfer
DACK
DMA acknowledge
I
DMA controller conrms the transfer;
also functions as data strobe
EOT
End-Of-Transfer
I
DMA controller terminates the transfer
RD
read strobe
I
not used
WR
write strobe
I
not used
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