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参数资料
| 型号： | ISPPAC-CLK5320S-01T64I |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 19/56页 |
| 文件大小： | 0K |
| 描述： | IC BUFFER FANOUT ISP UNIV 64TQFP |
| 标准包装： | 160 |
| 系列： | ispClock™ |
| 类型： | 时钟发生器，扇出配送，零延迟缓冲器 |
| PLL： | 带旁路 |
| 输入： | HSTL，LVCMOS，LVDS，LVPECL，LVTTL，SSTL |
| 输出： | eHSTL，HSTL，LVCMOS，LVTTL，SSTL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:20 |
| 差分 - 输入:输出： | 是/无 |
| 频率 - 最大： | 267MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-TQFP（10x10） |
| 包装： | 托盘 |
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Lattice Semiconductor
ispClock5300S Family Data Sheet
26
Figure 21. Conguration for SSTL2, SSTL3, and HSTL Output Modes
ispClock5300S Congurations
The ispClock5300S device can be congured to operate in four modes. They are:
Zero Delay Buffer Mode
Mixed Zero Delay and Non-Zero Delay Buffer Mode
Non-Zero Delay Buffer mode 1
Non-Zero Delay Buffer Mode 2
The output routing matrix of the ispClock5300S provides up to three independent any-to-any paths from inputs to
outputs:
From any V-Dividers to any output in ZDB mode or PLL Bypass modes
From selected clock via REFSEL pin to any output (note single ended reference clock)
From the other clock not selected by REFSEL pin to any output
Zero Delay Buffer Mode
Figure 22 shows the ispClock5300S device congured to operate in the Zero Delay Buffer mode. The Clock input
can be single ended or differential. Two single ended clocks can be selected by the use of REFSEL pin and if the
input is congured as a differential the REFSEL pin should be connected to GNDD. The input clock then drives the
Phase frequency detector of the PLL. Up to 3 output clock frequencies can be generated from the input reference
clock by the use of V-dividers at the output of PLL. Any V-divider output can be connected to any of the output pins.
However, one of the V-dividers should be used in the feedback path to set the PLL operating frequency. The PLL
can operate with internal or external feedback path.
In this mode, the skew control mechanism is active for all outputs.
Zo=50
Ro : 40 (SSTL)
20 (HSTL, eHSTL)
ispClock5300S
SSTL/HSTL/eHSTL
Mode
SSTL/HSTL/eHSTL
Receiver
VTT
VREF
RT=50
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISPPACCLK5320S-01T64I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ISPPACCLK5320S-01TN48C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ISPPACCLK5320S-01TN48I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ispPAC-CLK5320S-01TN64C | 功能描述:时钟驱动器及分配 ISP 0 Delay Unv Fan- Out Buf-Sngl End RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| ISPPACCLK5320S-01TN64C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
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