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参数资料
| 型号： | ISPPAC-CLK5320S-01T64I |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 33/56页 |
| 文件大小： | 0K |
| 描述： | IC BUFFER FANOUT ISP UNIV 64TQFP |
| 标准包装： | 160 |
| 系列： | ispClock™ |
| 类型： | 时钟发生器，扇出配送，零延迟缓冲器 |
| PLL： | 带旁路 |
| 输入： | HSTL，LVCMOS，LVDS，LVPECL，LVTTL，SSTL |
| 输出： | eHSTL，HSTL，LVCMOS，LVTTL，SSTL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:20 |
| 差分 - 输入:输出： | 是/无 |
| 频率 - 最大： | 267MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-TQFP（10x10） |
| 包装： | 托盘 |
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Lattice Semiconductor
ispClock5300S Family Data Sheet
39
For ispClock5300S, the instruction word length is eight bits. All ispClock5300S instructions available to users are
shown in Table 4.
The following table lists the instructions supported by the ispClock5300S JTAG Test Access Port (TAP) controller:
Table 4. ispClock5300S TAP Instruction Table
BYPASS is one of the three required instructions. It selects the Bypass Register to be connected between TDI and
TDO and allows serial data to be transferred through the device without affecting the operation of the
ispClock5300S. The IEEE 1149.1 standard denes the bit code of this instruction to be all ones (111111).
The required SAMPLE/PRELOAD instruction dictates the Boundary-Scan Register be connected between TDI
and TDO. The bit code for this instruction is dened by Lattice as shown in Table 4.
The EXTEST (external test) instruction is required and will place the device into an external boundary test mode
while also enabling the boundary scan register to be connected between TDI and TDO. The bit code of this instruc-
tion is dened by the 1149.1 standard to be all zeros (000000).
The optional IDCODE (identication code) instruction is incorporated in the ispClock5300S and leaves it in its func-
tional mode when executed. It selects the Device Identication Register to be connected between TDI and TDO.
The Identication Register is a 32-bit shift register containing information regarding the IC manufacturer, device
type and version code (Figure 34). Access to the Identication Register is immediately available, via a TAP data
scan operation, after power-up of the device, or by issuing a Test-Logic-Reset instruction. The bit code for this
instruction is dened by Lattice as shown in Table 4.
Instruction
Code
Description
EXTEST
0000 0000
External Test.
ADDRESS_SHIFT
0000 0001
Address register (10 bits)
DATA_SHIFT
0000 0010
Address column data register (42 bits for ispClock5312S, 5308S and 5304S;
61 bits for ispClock5320S and 5316S)
BULK_ERASE
0000 0011
Bulk Erase
PROGRAM
0000 0111
Program column data register to E
2
PROGRAM_SECURITY
0000 1001
Program Electronic Security Fuse
VERIFY
0000 1010
Verify column
DISCHARGE
0001 0100
Fast VPP Discharge
PROGRAM_ENABLE
0001 0101
Enable Program Mode
IDCODE
0001 0110
Address Manufacturer ID code register (32 bits)
USERCODE
0001 0111
Read UES data from E
2 and addresses UES register (32 bits)
PROGRAM_USERCODE
0001 1010
Program UES register into E
2
PROGRAM_DISABLE
0001 1110
Disable Program Mode
HIGHZ
0001 1000
Force all outputs to High-Z state
SAMPLE/PRELOAD
0001 1100
Capture current state of pins to boundary scan register
CLAMP
0010 0000
Drive I/Os with boundary scan register
INTEST
0010 1100
Performs in-circuit functional testing of device.
ERASE DONE
0010 0100
Erases the ‘Done’ bit only
PROG_INCR
0010 0111
Program column data register to E
2 and auto-increment address register
VERIFY_INCR
0010 1010
Load column data register from E
2 and auto-increment address register
PROGRAM_DONE
0010 1111
Programs the ‘Done’ Bit
NOOP
0011 0000
Functions Similarly to CLAMP instruction
BYPASS
1xxx xxxx
Bypass - Connect TDO to TDI
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISPPACCLK5320S-01T64I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ISPPACCLK5320S-01TN48C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ISPPACCLK5320S-01TN48I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ispPAC-CLK5320S-01TN64C | 功能描述:时钟驱动器及分配 ISP 0 Delay Unv Fan- Out Buf-Sngl End RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| ISPPACCLK5320S-01TN64C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
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