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参数资料
| 型号： | ISPPAC-CLK5320S-01T64I |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 28/56页 |
| 文件大小： | 0K |
| 描述： | IC BUFFER FANOUT ISP UNIV 64TQFP |
| 标准包装： | 160 |
| 系列： | ispClock™ |
| 类型： | 时钟发生器，扇出配送，零延迟缓冲器 |
| PLL： | 带旁路 |
| 输入： | HSTL，LVCMOS，LVDS，LVPECL，LVTTL，SSTL |
| 输出： | eHSTL，HSTL，LVCMOS，LVTTL，SSTL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:20 |
| 差分 - 输入:输出： | 是/无 |
| 频率 - 最大： | 267MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-TQFP（10x10） |
| 包装： | 托盘 |
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Lattice Semiconductor
ispClock5300S Family Data Sheet
34
Figure 29. External Feedback Mode and Timing Relationships
Other Features
RESET and Power-up Functions
To ensure proper PLL startup and synchronization of outputs, the ispClock5300S provides both internally gener-
ated and user-controllable external reset signals. An internal reset is generated whenever the device is powered
up. An external reset may be applied by asserting a logic LOW at the RESET pin. Asserting RESET resets all inter-
nal dividers, and will cause the PLL to lose lock. On losing lock, the VCO frequency will begin dropping. The length
of time required to regain lock is related to the length of time for which RESET was asserted.
When the ispClock5300S begins operating from initial power-on, the VCO starts running at a very low frequency
(<100 MHz) which gradually increases as it approaches a locked condition. To prevent invalid outputs from being
applied to the rest of the system, assert OEX or OEY high. This will result in the BANK outputs being held in a high-
impedance state until the OEX or OEY pin is pulled LOW.
After in-system programming the device through the JTAG interface, the reset pin must be activated at least for a
period of tPLL_RSTW to reset the device.
If the RESET pin is not driven by an external logic it should be pulled up to VCCD through a 10kΩ resistor.
Software-Based Design Environment
Designers can congure the ispClock5300S using Lattice’s PAC-Designer software, an easy to use, Microsoft Win-
dows compatible program. Circuit designs are entered graphically and then veried, all within the PAC-Designer envi-
ronment. Full device programming is supported using PC parallel port I/O operations and a download cable
connected to the serial programming interface pins of the ispClock5300S. A library of congurations is included with
basic solutions and examples of advanced circuit techniques are available. In addition, comprehensive on-line and
printed documentation is provided that covers all aspects of PAC-Designer operation. PAC-Designer is available for
download from the Lattice web site at www.latticesemi.com. The PAC-Designer schematic window, shown in
Figure 30 provides access to all congurable ispClock5300S elements via its graphical user interface. All analog input
and output pins are represented. Static or non-congurable pins such as power, ground and the serial digital interface
are omitted for clarity. Any element in the schematic window can be accessed via mouse operations as well as menu
commands. When completed, congurations can be saved and downloaded to devices.
Input Reference Clock
REF
FBK
BANK
OUTPUT
ispClock5300S
Delay = t
FBK
tφ
t
FBK
REF
FBK
BANK
OUTPUT
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISPPACCLK5320S-01T64I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ISPPACCLK5320S-01TN48C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ISPPACCLK5320S-01TN48I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ispPAC-CLK5320S-01TN64C | 功能描述:时钟驱动器及分配 ISP 0 Delay Unv Fan- Out Buf-Sngl End RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| ISPPACCLK5320S-01TN64C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
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