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| 型号： | ISPPAC-CLK5320S-01T64I |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 31/56页 |
| 文件大小： | 0K |
| 描述： | IC BUFFER FANOUT ISP UNIV 64TQFP |
| 标准包装： | 160 |
| 系列： | ispClock™ |
| 类型： | 时钟发生器，扇出配送，零延迟缓冲器 |
| PLL： | 带旁路 |
| 输入： | HSTL，LVCMOS，LVDS，LVPECL，LVTTL，SSTL |
| 输出： | eHSTL，HSTL，LVCMOS，LVTTL，SSTL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:20 |
| 差分 - 输入:输出： | 是/无 |
| 频率 - 最大： | 267MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-TQFP（10x10） |
| 包装： | 托盘 |
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Lattice Semiconductor
ispClock5300S Family Data Sheet
37
Figure 32. ispClock5300S TAP Registers
TAP Controller Specics
The TAP is controlled by the Test Clock (TCK) and Test Mode Select (TMS) inputs. These inputs determine whether
an Instruction Register or Data Register operation is performed. Driven by the TCK input, the TAP consists of a
small 16-state controller design. In a given state, the controller responds according to the level on the TMS input as
shown in Figure 33. Test Data In (TDI) and TMS are latched on the rising edge of TCK, with Test Data Out (TDO)
becoming valid on the falling edge of TCK. There are six steady states within the controller: Test-Logic-Reset, Run-
Test/Idle, Shift-Data-Register, Pause-Data-Register, Shift-Instruction-Register and Pause-Instruction-Register. But
there is only one steady state for the condition when TMS is set high: the Test-Logic-Reset state. This allows a
reset of the test logic within ve TCKs or less by keeping the TMS input high. Test-Logic-Reset is the power-on
default state.
Address Register (10 Bits)
E2CMOS
Non-Volatile
Memory
UES Register (32 Bits)
IDCODE Register (32 Bits)
Bypass Register (1 Bit)
Instruction Register (8 Bits)
Test Acess Port (TAP)
Logic
Output
Latch
TDI
TCK
TMS
TDO
Multiplexer
Data Register
(42 Bits for ispClock5312S, 5308S 5304S,
61 Bits for ispClock5320S and 5316S)
Boundary Scan Register
(34 Bits for ispClock5312S, 5308S, 5304S,
50 Bits for ispClock5320S and 5316S)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISPPACCLK5320S-01T64I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ISPPACCLK5320S-01TN48C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ISPPACCLK5320S-01TN48I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ispPAC-CLK5320S-01TN64C | 功能描述:时钟驱动器及分配 ISP 0 Delay Unv Fan- Out Buf-Sngl End RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| ISPPACCLK5320S-01TN64C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
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