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| 型号： | LC4032ZE-7TN48I |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 中文描述： | EE PLD, 7.5 ns, PQFP48 |
| 封装： | LEAD FREE, TQFP-48 |
| 文件页数： | 1/60页 |
| 文件大小： | 1381K |
| 代理商： | LC4032ZE-7TN48I |
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1
DS1022_01.4
ispMACH 4000ZE Family
1.8V In-System Programmable
Ultra Low Power PLDs
May 2009
Data Sheet DS1022
2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specications and information herein are subject to change without notice.
Features
■ High Performance
fMAX = 260MHz maximum operating frequency
tPD = 4.4ns propagation delay
Up to four global clock pins with programmable
clock polarity control
Up to 80 PTs per output
■ Ease of Design
Flexible CPLD macrocells with individual clock,
reset, preset and clock enable controls
Up to four global OE controls
Individual local OE control per I/O pin
Excellent First-Time-Fit
TM and ret
Wide input gating (36 input logic blocks) for fast
counters, state machines and address decoders
■ Ultra Low Power
Standby current as low as 10A typical
1.8V core; low dynamic power
Operational down to 1.6V VCC
Superior solution for power sensitive consumer
applications
Per pin pull-up, pull-down or bus keeper
control*
Power Guard with multiple enable signals*
■ Broad Device Offering
32 to 256 macrocells
Multiple temperature range support
– Commercial: 0 to 90°C junction (Tj)
– Industrial: -40 to 105°C junction (Tj)
Space-saving ucBGA and csBGA packages*
■ Easy System Integration
Operation with 3.3V, 2.5V, 1.8V or 1.5V
LVCMOS I/O
5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI
interfaces
Hot-socketing support
Open-drain output option
Programmable output slew rate
3.3V PCI compatible
I/O pins with fast setup path
Input hysteresis*
1.8V core power supply
IEEE 1149.1 boundary scan testable
IEEE 1532 ISC compliant
1.8V In-System Programmable (ISP) using
Boundary Scan Test Access Port (TAP)
Pb-free package options (only)
On-chip user oscillator and timer*
*New enhanced features over original ispMACH 4000Z
Table 1. ispMACH 4000ZE Family Selection Guide
ispMACH 4032ZE
ispMACH 4064ZE
ispMACH 4128ZE
ispMACH 4256ZE
Macrocells
32
64
128
256
tPD (ns)
4.4
4.7
5.8
tS (ns)
2.2
2.5
2.9
tCO (ns)
3.0
3.2
3.8
fMAX (MHz)
260
241
200
Supply Voltages (V)
1.8V
Packages
1 (I/O + Dedicated Inputs)
48-Pin TQFP (7 x 7mm)
32+4
64-Ball csBGA (5 x 5mm)
32+4
48+4
64-Ball ucBGA (4 x 4mm)
48+4
100-Pin TQFP (14 x 14mm)
64+10
132-Ball ucBGA (6 x 6mm)
96+4
144-Pin TQFP (20 x 20mm)
96+4
96+14
144-Ball csBGA (7 x 7mm)
64+10
96+4
108+4
1. Pb-free only.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LC4032ZE7TN48IES | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs |
| LC4032ZE-7TN48IES | 功能描述:CPLD - 复杂可编程逻辑器件 36 I/O 1.8V 7.5ns Ultra Low Power RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| LC4032ZE7TN64C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs |
| LC4032ZE7TN64CES | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs |
| LC4032ZE7TN64I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs |
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