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| 型号： | LC4032ZE-7TN48I |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 中文描述： | EE PLD, 7.5 ns, PQFP48 |
| 封装： | LEAD FREE, TQFP-48 |
| 文件页数： | 6/60页 |
| 文件大小： | 1381K |
| 代理商： | LC4032ZE-7TN48I |
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
14
Figure 13. On-Chip Oscillator and Timer
Table 11. On-Chip Oscillator and Timer Signal Names
OSCTIMER has two outputs, OSCOUT and TIMEROUT. The outputs feed into the Global Routing Pool (GRP).
From GRP, these signals can drive any macrocell input, as well as any output pin (with macrocell bypass). The out-
put OSCOUT is the direct oscillator output with a typical frequency of 5MHz, whereas, the output TIMEROUT is the
oscillator output divided by an attribute TIMER_DIV.
The attribute TIMER_DIV can be: 128 (7 bits), 1024 (10 bits) or 1,048,576 (20 bits). The divided output is provided
for those user situations, where a very slow clock is desired. If even a slower toggling clock is desired, then the pro-
grammable macrocell resources can be used to further divide down the TIMEROUT output.
Figure 14 shows the simplied relationship among OSCOUT, TIMERRES and TIMEROUT. In the diagram, the sig-
nal “R” is an internal reset signal that is used to synchronize TIMERRES to OSCOUT. This adds one extra clock
cycle delay for the rst timer transition after TIMERRES.
Figure 14. Relationship Among OSCOUT, TIMERRES and TIMEROUT
Signal Name
Input or Out-
put
Optional /
Required
Description
OSCOUT
Output
Optional
Oscillator Output (Nominal Frequency: 5MHz)
TIMEROUT
Output
Optional
Oscillator Frequency Divided by an integer TIMER_DIV (Default 128)
TIMERRES
Input
Optional
Reset the Timer
DYNOSCDIS
Input
Optional
Disables the Oscillator, resets the Timer and saves the power.
OSCTIMER
OSCOUT
TIMEROUT
TIMERRES
DYNOSCDIS
Note: n = Number of bits in the divider (7, 10 or 20)
Metastability: If the signal TIMERRES is not synchronous to OSCOUT, it could make a
difference of one or two clock cycles to the TIMEROUT going high the first time.
OSCOUT
22n / 2
2n
1
0
-1
TIMERRES
TIMEROUT
R (Internal)
MPW
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LC4032ZE7TN48IES | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs |
| LC4032ZE-7TN48IES | 功能描述:CPLD - 复杂可编程逻辑器件 36 I/O 1.8V 7.5ns Ultra Low Power RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| LC4032ZE7TN64C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs |
| LC4032ZE7TN64CES | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs |
| LC4032ZE7TN64I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs |
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