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参数资料
| 型号： | LC4032ZE-7TN48I |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 中文描述： | EE PLD, 7.5 ns, PQFP48 |
| 封装： | LEAD FREE, TQFP-48 |
| 文件页数： | 12/60页 |
| 文件大小： | 1381K |
| 代理商： | LC4032ZE-7TN48I |
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
2
Introduction
The high performance ispMACH 4000ZE family from Lattice offers an ultra low power CPLD solution. The new fam-
ily is based on Lattice’s industry-leading ispMACH 4000 architecture. Retaining the best of the previous generation,
the ispMACH 4000ZE architecture focuses on signicant innovations to combine high performance with low power
in a exible CPLD family. For example, the family’s new Power Guard feature minimizes dynamic power consump-
tion by preventing internal logic toggling due to unnecessary I/O pin activity.
The ispMACH 4000ZE combines high speed and low power with the exibility needed for ease of design. With its
robust Global Routing Pool and Output Routing Pool, this family delivers excellent First-Time-Fit, timing predictabil-
ity, routing, pin-out retention and density migration.
The ispMACH 4000ZE family offers densities ranging from 32 to 256 macrocells. There are multiple density-I/O
combinations in Thin Quad Flat Pack (TQFP), Chip Scale BGA (csBGA), and Ultra Chip Scale BGA (ucBGA) pack-
ages ranging from 32 to 144 pins/balls. Table 1 shows the macrocell, package and I/O options, along with other key
parameters.
A user programmable internal oscillator and a timer are included in the device for tasks like LED control, keyboard
scanner and similar housekeeping type state machines. This feature can be optionally disabled to save power.
The ispMACH 4000ZE family has enhanced system integration capabilities. It supports a 1.8V supply voltage and
3.3V, 2.5V, 1.8V and 1.5V interface voltages. Additionally, inputs can be safely driven up to 5.5V when an I/O bank
is congured for 3.3V operation, making this family 5V tolerant. The ispMACH 4000ZE also offers enhanced I/O
features such as slew rate control, PCI compatibility, bus-keeper latches, pull-up resistors, pull-down resistors,
open drain outputs and hot socketing. Pull-up, pull-down and bus-keeper features are controllable on a “per-pin”
basis. The ispMACH 4000ZE family members are 1.8V in-system programmable through the IEEE Standard 1532
interface. IEEE Standard 1149.1 boundary scan testing capability also allows product testing on automated test
equipment. The 1532 interface signals TCK, TMS, TDI and TDO are referenced to VCC (logic core).
Overview
The ispMACH 4000ZE devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks (GLBs) intercon-
nected by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O Blocks (IOBs),
which contain multiple I/O cells. This architecture is shown in Figure 1.
Figure 1. Functional Block Diagram
I/O
Block
ORP
16
OSC
16
GOE0
GOE1
V
CC
GND
TCK
TMS
TDI
TDO
36
Generic
Logic
Block
Generic
Logic
Block
I/O
Block
ORP
16
36
Generic
Logic
Block
Generic
Logic
Block
I/O
Block
I/O
Bank
0
I/O
Bank
1
I/O
Block
36
CLK0/I
CLK1/I
CLK2/I
CLK3/I
16
Global
Routing
Pool
V
CCO0
GND
V
CCO1
GND
16
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LC4032ZE7TN48IES | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs |
| LC4032ZE-7TN48IES | 功能描述:CPLD - 复杂可编程逻辑器件 36 I/O 1.8V 7.5ns Ultra Low Power RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| LC4032ZE7TN64C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs |
| LC4032ZE7TN64CES | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs |
| LC4032ZE7TN64I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs |
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