参数资料
型号: LC4032ZE-7TN48I
厂商: LATTICE SEMICONDUCTOR CORP
元件分类: PLD
中文描述: EE PLD, 7.5 ns, PQFP48
封装: LEAD FREE, TQFP-48
文件页数: 16/60页
文件大小: 1381K
代理商: LC4032ZE-7TN48I
Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
23
Timing Model
The task of determining the timing through the ispMACH 4000ZE family, like any CPLD, is relatively simple. The
timing model provided in Figure 16 shows the specic delay paths. Once the implementation of a given function is
determined either conceptually or from the software report le, the delay path of the function can easily be deter-
mined from the timing model. The Lattice design tools report the timing delays based on the same timing model for
a particular design. Note that the internal timing parameters are given for reference only, and are not tested. The
external timing parameters are tested and guaranteed for every device. For more information on the timing model
Figure 16. ispMACH 4000ZE Timing Model
DATA
MC Reg.
C.E.
S/R
Q
SCLK
IN
OE
In/Out
Delays
Oscillator/ Timer
Delays
In/Out
Delays
Control
Delays
Register/Latch
Delays
Routing/GLB Delays
Out
Note: Italicized items are optional delay adders.
tFBK
Feedback
From
Feedback
tBUF
tMCELL
tPTCLK
tBCLK
tPTSR
tBIE
tBSR
tGPTOE
tPTOE
tEXP
tROUTE
tOSCDIS
tOSCEN
tOSCOD
tBLA
tINREG
tINDIO
tIN
tPGRT
tIOI
tGCLK_IN
tIOI
tPGRT
tGOE
tIOI
tPDi
tIOO
tORP
tEN
tDIS
相关PDF资料
PDF描述
LC4256B-3FT256AC
LC4256C-75F256AC
LC4128B-75T128C
LC4128ZC-75T100I
LC4384C-75T176I
相关代理商/技术参数
参数描述
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