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| 型号： | LC4032ZE-7TN48I |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 中文描述： | EE PLD, 7.5 ns, PQFP48 |
| 封装： | LEAD FREE, TQFP-48 |
| 文件页数： | 59/60页 |
| 文件大小： | 1381K |
| 代理商： | LC4032ZE-7TN48I |
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
8
Output Routing Pool (ORP)
The Output Routing Pool allows macrocell outputs to be connected to any of several I/O cells within an I/O block.
This provides greater exibility in determining the pinout and allows design changes to occur without affecting the
pinout. The output routing pool also provides a parallel capability for routing macrocell-level OE product terms. This
allows the OE product term to follow the macrocell output as it is switched between I/O cells. The enhanced ORP of
the ispMACH 4000ZE family consists of the following elements:
Output Routing Multiplexers
OE Routing Multiplexers
Figure 7 shows the structure of the ORP from the I/O cell perspective. This is referred to as an ORP slice. Each
ORP has as many ORP slices as there are I/O cells in the corresponding I/O block.
Figure 7. ORP Slice
Output Routing Multiplexers
The details of connections between the macrocells and the I/O cells vary across devices and within a device
dependent on the maximum number of I/Os available. Tables 5-7 provide the connection details.
Table 5. GLB/MC/ORP Combinations for ispMACH 4256ZE
GLB/MC
ORP Mux Input Macrocells
[GLB] [MC 0]
M0, M1, M2, M3, M4, M5, M6, M7
[GLB] [MC 1]
M2, M3, M4, M5, M6, M7, M8, M9
[GLB] [MC 2]
M4, M5, M6, M7, M8, M9, M10, M11
[GLB] [MC 3]
M6, M7, M8, M9, M10, M11, M12, M13
[GLB] [MC 4]
M8, M9, M10, M11, M12, M13, M14, M15
[GLB] [MC 5]
M10, M11, M12, M13, M14, M15, M0, M1
[GLB] [MC 6]
M12, M13, M14, M15, M0, M1, M2, M3
[GLB] [MC 7]
M14, M15, M0, M1, M2, M3, M4, M5
Output Routing Multiplexer
OE Routing Multiplexer
From Macrocell
From PTOE
To I/O
Cell
To I/O
Cell
OE
相关PDF资料 |
PDF描述 |
|---|---|
| LC4256B-3FT256AC | |
| LC4256C-75F256AC | |
| LC4128B-75T128C | |
| LC4128ZC-75T100I | |
| LC4384C-75T176I | |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LC4032ZE7TN48IES | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs |
| LC4032ZE-7TN48IES | 功能描述:CPLD - 复杂可编程逻辑器件 36 I/O 1.8V 7.5ns Ultra Low Power RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| LC4032ZE7TN64C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs |
| LC4032ZE7TN64CES | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs |
| LC4032ZE7TN64I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs |
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