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参数资料
| 型号： | LC4032ZE-7TN48I |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 中文描述： | EE PLD, 7.5 ns, PQFP48 |
| 封装： | LEAD FREE, TQFP-48 |
| 文件页数： | 8/60页 |
| 文件大小： | 1381K |
| 代理商： | LC4032ZE-7TN48I |
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Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
16
Table 12. OSC and TIMER MC Designation
Zero Power/Low Power and Power Management
The ispMACH 4000ZE family is designed with high speed low power design techniques to offer both high speed
and low power. With an advanced E
2 low power cell and non sense-amplier design approach (full CMOS logic
approach), the ispMACH 4000ZE family offers fast pin-to-pin speeds, while simultaneously delivering low standby
power without needing any “turbo bits” or other power management schemes associated with a traditional sense-
amplier approach.
The zero power ispMACH 4000ZE is based on the 1.8V ispMACH 4000Z family. With innovative circuit design
changes, the ispMACH 4000ZE family is able to achieve the industry’s lowest static power.
IEEE 1149.1-Compliant Boundary Scan Testability
All ispMACH 4000ZE devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This
allows functional testing of the circuit board on which the device is mounted through a serial scan path that can
access all critical logic notes. Internal registers are linked internally, allowing test data to be shifted in and loaded
directly onto test nodes, or test node data to be captured and shifted out for verication. In addition, these devices
can be linked into a board-level serial scan path for more board-level testing. The test access port operates with an
LVCMOS interface that corresponds to the power supply voltage.
I/O Quick Conguration
To facilitate the most efcient board test, the physical nature of the I/O cells must be set before running any continu-
ity tests. As these tests are fast, by nature, the overhead and time that is required for conguration of the I/Os’
physical nature should be minimal so that board test time is minimized. The ispMACH 4000ZE family of devices
allows this by offering the user the ability to quickly congure the physical nature of the I/O cells. This quick cong-
uration takes milliseconds to complete, whereas it takes seconds for the entire device to be programmed. Lattice's
ispVM System programming software can either perform the quick conguration through the PC parallel port, or
can generate the ATE or test vectors necessary for a third-party test system.
IEEE 1532-Compliant In-System Programming
Programming devices in-system provides a number of signicant benets including: rapid prototyping, lower inven-
tory levels, higher quality and the ability to make in-eld modications. All ispMACH 4000ZE devices provide In-
System Programming (ISP) capability through the Boundary Scan Test Access Port. This capability has been
implemented in a manner that ensures that the port remains complaint to the IEEE 1149.1 standard. By using IEEE
1149.1 as the communication interface through which ISP is achieved, users get the benet of a standard, well-
dened interface. All ispMACH 4000ZE devices are also compliant with the IEEE 1532 standard.
The ispMACH 4000ZE devices can be programmed across the commercial temperature and voltage range. The
PC-based Lattice software facilitates in-system programming of ispMACH 4000ZE devices. The software takes the
JEDEC le output produced by the design implementation software, along with information about the scan chain,
and creates a set of vectors used to drive the scan chain. The software can use these vectors to drive a scan chain
via the parallel port of a PC. Alternatively, the software can output les in formats understood by common auto-
Device
Macrocell
Block Number
MC Number
ispMACH 4032ZE
OSC MC
TIMER MC
A
B
15
ispMACH 4064ZE
OSC MC
TIMER MC
A
D
15
ispMACH 4128ZE
OSC MC
TIMER MC
A
G
15
ispMACH 4256ZE
OSC MC
TIMER MC
C
F
15
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| LC4256B-3FT256AC | |
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| LC4128B-75T128C | |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LC4032ZE7TN48IES | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs |
| LC4032ZE-7TN48IES | 功能描述:CPLD - 复杂可编程逻辑器件 36 I/O 1.8V 7.5ns Ultra Low Power RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| LC4032ZE7TN64C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs |
| LC4032ZE7TN64CES | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs |
| LC4032ZE7TN64I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs |
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