参数资料
型号: LFX200EB-03F256C
厂商: Lattice Semiconductor Corporation
文件页数: 24/119页
文件大小: 0K
描述: IC FPGA 200K GATES 256-BGA
标准包装: 90
系列: ispXPGA®
逻辑元件/单元数: 2704
RAM 位总计: 113664
输入/输出数: 160
门数: 210000
电源电压: 2.3 V ~ 3.6 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 256-BGA
供应商设备封装: 256-FPBGA(17x17)
Lattice Semiconductor
ispXPGA Family Data Sheet
8
Figure 6. ispXPGA Wide Logic Generator
Configurable Sequential Element
There are two registers in each CSE for a total of eight registers in each PFU. This high register count assists in
implementing efficient pipelined applications with no utilization penalty. Each register can be configured as a latch
or D type flip-flop with either synchronous or asynchronous set or reset. Figure 2 shows the signals that feed the
register’s D inputs. Feed-through signals in the architecture ensure that registers are efficiently utilized even if the
accompanying LUT is occupied.
Control Logic
The control signals available to the registers in a PFU are Clock, Clock Enable, and Set/Reset. Figure 7 shows the
various options available to generate the clock signal. As can be seen, the clock signal is the output of a 12:1 MUX
with true and compliment versions available from the 12:1 MUX. Each CSE can chose whether it uses the true or
complement form of the clock. Figure 8 shows the Set/Reset selection for each PFU in the ispXPGA. A common
4B
S2
4C
S1
4D
S0
COUT
WLGW0
WLGW1
WLGX0
WLGX1
WLGY0
WLGY1
WLGZ0
WLGZ1
4A
S3
SEL0
SEL1
SEL2
WIN2
WIN3
XIN2
XIN3
YIN2
YIN3
ZIN2
ZIN3
SEL3
SELECT
DEVICES
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