- 您现在的位置：买卖IC网 > PDF目录299403 > LFXP15C-4FN256C (LATTICE SEMICONDUCTOR CORP) PDF资料下载
参数资料
| 型号： | LFXP15C-4FN256C |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 中文描述： | FPGA, 1932 CLBS, PBGA256 |
| 封装： | 17 X 17 MM, LEAD FREE, FPBGA-256 |
| 文件页数： | 49/130页 |
| 文件大小： | 1312K |
| 代理商： | LFXP15C-4FN256C |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页当前第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页
2-22
Architecture
Lattice Semiconductor
LatticeXP Family Data Sheet
Polarity Control Logic
In a typical DDR Memory interface design, the phase relation between the incoming delayed DQS strobe and the
internal system Clock (during the READ cycle) is unknown.
The LatticeXP family contains dedicated circuits to transfer data between these domains. To prevent setup and
hold violations at the domain transfer between DQS (delayed) and the system Clock a clock polarity selector is
used. This changes the edge on which the data is registered in the synchronizing registers in the input register
block. This requires evaluation at the start of the each READ cycle for the correct clock polarity.
Prior to the READ operation in DDR memories DQS is in tristate (pulled by termination). The DDR memory device
drives DQS low at the start of the preamble state. A dedicated circuit detects this transition. This signal is used to
control the polarity of the clock to the synchronizing registers.
sysIO Buffer
Each I/O is associated with a flexible buffer referred to as a sysIO buffer. These buffers are arranged around the
periphery of the device in eight groups referred to as Banks. The sysIO buffers allow users to implement the wide
variety of standards that are found in today’s systems including LVCMOS, SSTL, HSTL, LVDS and LVPECL.
sysIO Buffer Banks
LatticeXP devices have eight sysIO buffer banks; each is capable of supporting multiple I/O standards. Each sysIO
bank has its own I/O supply voltage (VCCIO), and two voltage references VREF1 and VREF2 resources allowing each
bank to be completely independent from each other. Figure 2-28 shows the eight banks and their associated sup-
plies.
In the LatticeXP devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS, PCI and PCI-X) are
powered using VCCIO. LVTTL, LVCMOS33, LVCMOS25 and LVCMOS12 can also be set as a fixed threshold input
independent of VCCIO. In addition to the bank VCCIO supplies, the LatticeXP devices have a VCC core logic power sup-
ply, and a VCCAUX supply that power all differential and referenced buffers.
Each bank can support up to two separate VREF voltages, VREF1 and VREF2 that set the threshold for the refer-
enced input buffers. In the LatticeXP devices, a dedicated pin in a bank can be configured to be a reference voltage
supply pin. Each I/O is individually configurable based on the bank’s supply and reference voltages.
相关PDF资料 |
PDF描述 |
|---|---|
| LFZ3508VXX | GENERAL PURPOSE INDUCTOR |
| LFZ2805HXX | GENERAL PURPOSE INDUCTOR |
| LF02004VTX | GENERAL PURPOSE INDUCTOR |
| LG3341-NE7501 | T-1 SINGLE COLOR LED, GREEN, 3 mm |
| LG3341-KNE9117 | T-1 SINGLE COLOR LED, GREEN, 3 mm |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LFXP15C-4FN256I | 功能描述:FPGA - 现场可编程门阵列 15.4K LUTs 188 IO 1. 8/2.5/3.3V-4 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| LFXP15C-4FN388C | 功能描述:FPGA - 现场可编程门阵列 15.4K LUTs 268 IO 1. 8/2.5/3.3V -4 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| LFXP15C-4FN388I | 功能描述:FPGA - 现场可编程门阵列 15.4K LUTs 268 IO 1. 8/2.5/3.3V-4 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| LFXP15C-4FN484C | 功能描述:FPGA - 现场可编程门阵列 15.4K LUTs 1.8/2.5/3 .3V -4 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| LFXP15C-4FN484I | 功能描述:FPGA - 现场可编程门阵列 15.4K LUTs 1.8/2.5/3 .3V-4 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
发布紧急采购，3分钟左右您将得到回复。