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| 型号： | LFXP15C-4FN256C |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 中文描述： | FPGA, 1932 CLBS, PBGA256 |
| 封装： | 17 X 17 MM, LEAD FREE, FPBGA-256 |
| 文件页数： | 53/130页 |
| 文件大小： | 1312K |
| 代理商： | LFXP15C-4FN256C |
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2-26
Architecture
Lattice Semiconductor
LatticeXP Family Data Sheet
Table 2-9. Characteristics of Normal, Off and Sleep Modes
SLEEPN Pin Characteristics
The SLEEPN pin behaves as an LVCMOS input with the voltage standard appropriate to the VCC supply for the
device. This pin also has a weak pull-up typically in the order of 10A along with a Schmidt trigger and glitch filter
to prevent false triggering. An external pull-up to VCC is recommended when Sleep Mode is not used to ensure the
device stays in normal operation mode. Typically the device enters Sleep Mode several hundred ns after SLEEPN
is held at a valid low and restarts normal operation as specified in the Sleep Mode Timing table. The AC and DC
specifications portion of this data sheet show a detailed timing diagram.
Configuration and Testing
The following section describes the configuration and testing features of the LatticeXP family of devices.
IEEE 1149.1-Compliant Boundary Scan Testability
All LatticeXP devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test access
port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan
path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in
and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port
consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage VCCJ and can
operate with LVCMOS3.3, 2.5, 1.8, 1.5 and 1.2 standards.
For more details on boundary scan test, please see information regarding additional technical documentation at
the end of this data sheet.
Device Configuration
All LatticeXP devices contain two possible ports that can be used for device configuration and programming. The
test access port (TAP), which supports serial configuration, and the sysCONFIG port that supports both byte-wide
and serial configuration.
The non-volatile memory in the LatticeXP can be configured in three different modes:
In sysCONFIG mode via the sysCONFIG port. Note this can also be done in background mode.
In 1532 mode via the 1149.1 port.
In background mode via the 1149.1 port. This allows the device to be operated while reprogramming takes
place.
The SRAM configuration memory can be configured in three different ways:
At power-up via the on-chip non-volatile memory.
In 1532 mode via the 1149.1 port SRAM direct configuration.
In sysCONFIG mode via the sysCONFIG port SRAM direct configuration.
Characteristic
Normal
Off
Sleep
SLEEPN Pin
High
—
Low
Static Icc
Typical <100mA
0
Typical <100uA
I/O Leakage
<10A
<1mA
<10A
Power Supplies VCC/VCCIO/VCCAUX
Normal Range
Off
Normal Range
Logic Operation
User Defined
Non Operational
Non operational
I/O Operation
User Defined
Tri-state
JTAG and Programming circuitry
Operational
Non-operational
EBR Contents and Registers
Maintained
Non-maintained
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LFXP15C-4FN256I | 功能描述:FPGA - 现场可编程门阵列 15.4K LUTs 188 IO 1. 8/2.5/3.3V-4 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| LFXP15C-4FN388C | 功能描述:FPGA - 现场可编程门阵列 15.4K LUTs 268 IO 1. 8/2.5/3.3V -4 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| LFXP15C-4FN388I | 功能描述:FPGA - 现场可编程门阵列 15.4K LUTs 268 IO 1. 8/2.5/3.3V-4 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| LFXP15C-4FN484C | 功能描述:FPGA - 现场可编程门阵列 15.4K LUTs 1.8/2.5/3 .3V -4 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| LFXP15C-4FN484I | 功能描述:FPGA - 现场可编程门阵列 15.4K LUTs 1.8/2.5/3 .3V-4 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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