参数资料
型号: LFXP15C-4FN256C
厂商: LATTICE SEMICONDUCTOR CORP
元件分类: FPGA
中文描述: FPGA, 1932 CLBS, PBGA256
封装: 17 X 17 MM, LEAD FREE, FPBGA-256
文件页数: 56/130页
文件大小: 1312K
代理商: LFXP15C-4FN256C
2-28
Architecture
Lattice Semiconductor
LatticeXP Family Data Sheet
master serial clock is 2.5MHz. Table 2-10 lists all the available Master Serial Clock frequencies. When a different
Master Serial Clock is selected during the design process, the following sequence takes place:
1.
User selects a different Master Serial Clock frequency for configuration.
2.
During configuration the device starts with the default (2.5MHz) Master Serial Clock frequency.
3.
The clock configuration settings are contained in the early configuration bit stream.
4.
The Master Serial Clock frequency changes to the selected frequency once the clock configuration bits are
received.
For further information on the use of this oscillator for configuration, please see details of additional technical docu-
mentation at the end of this data sheet.
Table 2-10. Selectable Master Serial Clock (CCLK) Frequencies During Configuration
Density Shifting
The LatticeXP family has been designed to ensure that different density devices in the same package have the
same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration from
lower density parts to higher density parts. In many cases, it is also possible to shift a lower utilization design tar-
geted for a high-density device to a lower density device. However, the exact details of the final resource utilization
will impact the likely success in each case.
CCLK (MHz)
2.5
1
13
45
4.3
15
51
5.4
20
55
6.9
26
60
8.1
30
130
9.2
34
10.0
41
1. Default
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