参数资料
型号: M25PE40VMW6G
厂商: STMICROELECTRONICS
元件分类: PROM
英文描述: 512K X 8 SPI BUS SERIAL EEPROM, PDSO8
封装: 0.208 INCH, ROHS COMPLIANT, PLASTIC, SOP-8
文件页数: 31/62页
文件大小: 565K
代理商: M25PE40VMW6G
M25PE40
Instructions
37/62
6.13
Subsector Erase (SSE)
Note:
The Subsector Erase (SSE) instruction is decoded only in the M25PE40 in the T9HX
The Subsector Erase (SSE) instruction sets to ‘1’ (FFh) all bits inside the chosen subsector.
Before it can be accepted, a Write Enable (WREN) instruction must previously have been
executed. After the Write Enable (WREN) instruction has been decoded, the device sets the
Write Enable Latch (WEL).
The Subsector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by
the instruction code, and three address bytes on Serial Data input (D). Any address inside
the Subsector (see Table 4) is a valid address for the Subsector Erase (SE) instruction. Chip
Select (S) must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 20.
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the Subsector Erase (SE) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed Subsector Erase cycle (whose duration is tSSE) is
initiated. While the Subsector Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Subsector Erase cycle, and is 0 when it is completed. At some
unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset.
A Subsector Erase (SSE) instruction applied to a subsector that contains a page that is
hardware or software protected is not executed.
Any Subsector Erase (SSE) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
If Reset (Reset) is driven Low while a Subsector Erase (SSE) cycle is in progress, the
Subsector Erase cycle is interrupted and data may not be erased correctly (see Table 12:
Device status after a Reset Low pulse). On Reset going Low, the device enters the Reset
mode and a time of tRHSL is then required before the device can be re-selected by driving
Chip Select (S) Low. For the value of tRHSL see Table 24: Timings after a Reset Low pulse in
Figure 19.
Subsector Erase (SSE) instruction sequence
1.
Address bits A23 to A19 are Don’t care.
24-bit address
C
D
AI12356
S
2
1
3456789
29 30 31
Instruction
0
23 22
20
1
MSB
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