- 您现在的位置：买卖IC网 > PDF目录180109 > M25PE40VMW6G (STMICROELECTRONICS) 512K X 8 SPI BUS SERIAL EEPROM, PDSO8 PDF资料下载
参数资料
| 型号： | M25PE40VMW6G |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | PROM |
| 英文描述： | 512K X 8 SPI BUS SERIAL EEPROM, PDSO8 |
| 封装： | 0.208 INCH, ROHS COMPLIANT, PLASTIC, SOP-8 |
| 文件页数： | 6/62页 |
| 文件大小： | 565K |
| 代理商： | M25PE40VMW6G |
第1页第2页第3页第4页第5页当前第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页
Operating features
M25PE40
4.7
Status Register
The Status Register contains a number of status and control bits that can be read or set (as
appropriate) by using specific instructions. See Section 6.4: Read Status Register (RDSR)
for a detailed description of the Status Register bits.
4.8
Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
features the following data protection mechanisms:
4.8.1
Protocol-related protections
●
Power On Reset and an internal timer (tPUW) can provide protection against inadvertent
changes while the power supply is outside the operating specification.
●
Program, Erase and Write instructions are checked that they consist of a number of
clock pulses that is a multiple of eight, before they are accepted for execution.
●
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–Power-up
–
Reset (Reset) driven Low
–
Write Disable (WRDI) instruction completion
–
Page Write (PW) instruction completion
–
Page Program (PP) instruction completion
–
Write to Lock Register (WRLR) instruction completion
–
Page Erase (PE) instruction completion
–
Subsector Erase (SSE) instruction completion
–
Sector Erase (SE) instruction completion
–
Bulk Erase (BE) instruction completion
●
The Reset (Reset) signal can be driven Low to freeze and reset the internal logic. For
the specific cases of Program and Write cycles, the designer should refer to
●
In addition to the low power consumption feature, the Deep Power-down mode offers
extra software protection from inadvertent Write, Program and Erase instructions while
the device is not in active use.
相关PDF资料 |
PDF描述 |
|---|---|
| M27C1024-10F1X | 1 Mbit 64Kb x16 UV EPROM and OTP EPROM |
| M27C1024-10F3TR | 1 Mbit 64Kb x16 UV EPROM and OTP EPROM |
| M27C1024-10F3X | 1 Mbit 64Kb x16 UV EPROM and OTP EPROM |
| M27C1024-10F6TR | 1 Mbit 64Kb x16 UV EPROM and OTP EPROM |
| M27C1024-10F6X | 1 Mbit 64Kb x16 UV EPROM and OTP EPROM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M25PE40-VMW6G | 功能描述:闪存 4 Mbit Lo Vltg Page Erasable Seral 闪存 RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| M25PE40-VMW6G_NUD | 制造商:Micron Technology Inc 功能描述: |
| M25PE40VMW6P | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:4 Mbit, low voltage, Page-Erasable Serial Flash memory with byte alterability, 50 MHz SPI bus, standard pinout |
| M25PE40-VMW6P | 制造商:NUMONYX 制造商全称:Numonyx B.V 功能描述:4 Mbit, page-erasable serial Flash memory with byte alterability, 75 MHz SPI bus, standard pinout |
| M25PE40VMW6TG | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:4 Mbit, low voltage, Page-Erasable Serial Flash memory with byte alterability, 50 MHz SPI bus, standard pinout |
发布紧急采购，3分钟左右您将得到回复。