参数资料
型号: M25PE40VMW6G
厂商: STMICROELECTRONICS
元件分类: PROM
英文描述: 512K X 8 SPI BUS SERIAL EEPROM, PDSO8
封装: 0.208 INCH, ROHS COMPLIANT, PLASTIC, SOP-8
文件页数: 37/62页
文件大小: 565K
代理商: M25PE40VMW6G
Power-up and power-down
M25PE40
7
Power-up and power-down
At power-up and power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on VCC) until VCC reaches the correct value:
VCC(min) at power-up, and then for a further delay of tVSL
VSS at power-down.
A safe configuration is provided in Section 3: SPI modes.
To avoid data corruption and inadvertent write operations during power-up, a Power On
Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less
than the Power On Reset (POR) threshold voltage, VWI – all operations are disabled, and
the device does not respond to any instruction.
Moreover, the device ignores all Write Enable (WREN), Page Write (PW), Page Program
(PP), Page Erase (PE) and Sector Erase (SE) instructions until a time delay of tPUW has
elapsed after the moment that VCC rises above the VWI threshold. However, the correct
operation of the device is not guaranteed if, by this time, VCC is still below VCC(min). No
Write, Program or Erase instructions should be sent until the later of:
tPUW after VCC passed the VWI threshold
tVSL after VCC passed the VCC(min) level.
These values are specified in Table 11.
If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be
selected for READ instructions even if the tPUW delay is not yet fully elapsed.
As an extra protection, the Reset (Reset) signal could be driven Low for the whole duration
of the power-up and power-down phases.
At power-up, the device is in the following state:
The device is in the Standby Power mode (not the Deep Power-down mode)
The Write Enable Latch (WEL) bit is reset
The Write In Progress (WIP) bit is reset
The Lock Registers are reset (Write Lock bit, Lock Down bit) = (0, 0).
Normal precautions must be taken for supply rail decoupling, to stabilize the VCC supply.
Each device in a system should have the VCC rail decoupled by a suitable capacitor close to
the package pins. (Generally, this capacitor is of the order of 100 nF).
At power-down, when VCC drops from the operating voltage, to below the Power On Reset
(POR) threshold voltage, VWI, all operations are disabled and the device does not respond
to any instruction. (The designer needs to be aware that if a Power-down occurs while a
Write, Program or Erase cycle is in progress, some data corruption can result.)
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