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参数资料
| 型号： | M295V100-T70XM3R |
| 厂商： | 意法半导体 |
| 元件分类： | FLASH |
| 英文描述： | 1 Mbit 128Kb x8 or 64Kb x16, Boot Block Single Supply Flash Memory |
| 中文描述： | 1兆位的128KBx8或64Kbx16，有启动区域的单电源闪存 |
| 文件页数： | 12/30页 |
| 文件大小： | 207K |
| 代理商： | M295V100-T70XM3R |
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AI01275B
3V
High Speed
0V
1.5V
2.4V
Standard
0.45V
2.0V
0.8V
Figure 4. AC TestingInput Output Waveform
AI01276B
1.3V
OUT
CL
CL= 30pF for High Speed
CL= 100pF for Standard
CLincludes JIG capacitance
3.3k
1N914
DEVICE
UNDER
TEST
Figure 5. AC TestingLoad Circuit
Symbol
Parameter
TestCondition
Min
Max
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
12
pF
Note:
1. Sampled only,not 100% tested.
Table12. Capacitance
(1)
(T
A
= 25
°
C, f = 1 MHz)
Block Erase (BE) Instruction
. This instruction
uses a minimum of six write cycles. The Erase
Set-upcommand80h is written to addressAAAAh
in the Byte-wideconfigurationor address5555h in
theWord-wideconfigurationon thirdcycleafter the
two Coded cycles. The Block Erase Confirm com-
mand30his similarlywrittenonthesixthcycleafter
anothertwo Coded cycles. During the inputof the
secondcommandan addresswithintheblockto be
erasedis given andlatchedintothememory.Addi-
tional block Erase Confirm commands and block
addresses can be written subsequently to erase
other blocks in parallel, without further Coded cy-
cles. The erase will start after the erase timeout
period (see Erase Timer Bit DQ3 description).
Thus, additional Erase Confirm commands for
other blocks must be given within this delay. The
inputof a newEraseConfirm commandwill restart
the timeout period. The status of the internaltimer
canbe monitoredthrough the levelof DQ3,if DQ3
is ’0’ the Block Erase Command has been given
andthe timeoutis running,ifDQ3is ’1’,thetimeout
hasexpiredand theP/E.C.is erasingtheBlock(s).
If the second command given is not an erase
confirm or if the Coded cycles are wrong, the
instruction aborts, and the device is reset to Read
Array. It is notnecessarytoprogramthe blockwith
00h as the P/E.C. will do this automaticallybefore
to erasing to FFh. Read operations after the sixth
rising edge of W or E output the status register
statusbits.
High Speed
Standard
Input Rise and Fall Times
≤
10ns
≤
10ns
Input Pulse Voltages
0 to 3V
0.45V to 2.4V
Input and Output Timing Ref. Voltages
1.5V
0.8V and 2V
Table11. ACMeasurementConditions
12/30
M29F100T, M29F100B
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M295V100-T70XM3TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:1 Mbit 128Kb x8 or 64Kb x16, Boot Block Single Supply Flash Memory |
| M295V100-T70XM6R | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:1 Mbit 128Kb x8 or 64Kb x16, Boot Block Single Supply Flash Memory |
| M295V100-T70XM6TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:1 Mbit 128Kb x8 or 64Kb x16, Boot Block Single Supply Flash Memory |
| M295V100-T70XN1R | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:1 Mbit 128Kb x8 or 64Kb x16, Boot Block Single Supply Flash Memory |
| M295V100-T70XN1TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:1 Mbit 128Kb x8 or 64Kb x16, Boot Block Single Supply Flash Memory |
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