参数资料
型号: M295V100-T70XM3R
厂商: 意法半导体
元件分类: FLASH
英文描述: 1 Mbit 128Kb x8 or 64Kb x16, Boot Block Single Supply Flash Memory
中文描述: 1兆位的128KBx8或64Kbx16,有启动区域的单电源闪存
文件页数: 14/30页
文件大小: 207K
代理商: M295V100-T70XM3R
Symbol
Alt
Parameter
Test Condition
M29F100T / M29F100B
Unit
-70
-90
-120
V
CC
= 5V
±
5% V
CC
= 5V
±
10% V
CC
= 5V
±
10%
High Speed
Interface
Standard
Interface
Standard
Interface
Min
Max
Min
Max
Min
Max
t
AVAV
t
RC
Address Valid to
Next Address Valid
E = V
IL
, G = V
IL
70
90
120
ns
t
AVQV
t
ACC
Address Valid to
Output Valid
E = V
IL
, G = V
IL
70
90
120
ns
t
ELQX
(1)
t
LZ
Chip Enable Low to
Output Transition
G = V
IL
0
0
0
ns
t
ELQV
(2)
t
CE
Chip Enable Low to
Output Valid
G = V
IL
70
90
120
ns
t
GLQX
(1)
t
OLZ
Output Enable Low
to Output Transition
E = V
IL
0
0
0
ns
t
GLQV
(2)
t
OE
Output Enable Low
to Output Valid
E = V
IL
30
35
50
ns
t
EHQX
t
OH
Chip Enable High to
Output Transition
G = V
IL
0
0
0
ns
t
EHQZ(1)
t
HZ
Chip Enable High to
Output Hi-Z
G = V
IL
20
20
30
ns
t
GHQX
t
OH
Output Enable High
to Output Transition
E = V
IL
0
0
0
ns
t
GHQZ
(1)
t
DF
Output Enable High
to Output Hi-Z
E = V
IL
20
20
30
ns
t
AXQX
t
OH
Address Transition to
Output Transition
E = V
IL
, G = V
IL
0
0
0
ns
t
PLYH(1,3)
t
RRB
t
READY
RP Low to Read
Mode
10
10
10
μ
s
t
PHEL
t
RH
RP High to Chip
Enable Low
50
50
50
ns
t
PLPX
t
RP
RP Pulse Width
500
500
500
ns
t
ELBL
t
ELBH
t
ELFL
t
ELFH
Chip Enable to BYTE
Switching Low or
High
5
5
5
ns
t
BLQZ
t
FLQZ
BYTE Switching Low
to Output
High Z
30
40
40
ns
t
BHQV
t
FHQV
BYTE Switching
High to Output
Valid
30
40
40
ns
Notes:
1. Sampled only,not 100% tested.
2. G may be delayed by up to t
- t
afterthe falling edge of E withoutincreasing t
.
3. Tobe considered only if the Reset pulse is given while the memory is in Erase or Program mode.
Table14. ReadAC Characteristics
(T
A
= 0 to 70
°
C, –40 to 85
°
C or–40 to 125
°
C)
14/30
M29F100T, M29F100B
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