参数资料
型号: M295V100-T70XM3R
厂商: 意法半导体
元件分类: FLASH
英文描述: 1 Mbit 128Kb x8 or 64Kb x16, Boot Block Single Supply Flash Memory
中文描述: 1兆位的128KBx8或64Kbx16,有启动区域的单电源闪存
文件页数: 3/30页
文件大小: 207K
代理商: M295V100-T70XM3R
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
(3)
–40 to 125
°
C
T
BIAS
Temperature Under Bias
–50 to 125
°
C
T
STG
V
IO(2)
Storage Temperature
–65 to 150
°
C
Input or Output Voltages
–0.6to 7
V
V
CC
Supply Voltage
–0.6to 7
V
V
(A9, E, G, RP)
(2)
A9, E, G, RP Voltage
–0.6to 13.5
V
Notes:
1. Except for therating ”Operating Temperature Range”, stresses above those listed in theTable ”AbsoluteMaximum Ratings”
may cause permanentdamage to thedevice. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operatingsections of this specification is not implied.Exposure to Absolute Maximum
Rating conditions for extendedperiods may affectdevice reliability.Refer also tothe STMicroelectronics SURE Program and other
relevant quality documents.
2. Minimum Voltagemay undershoot to –2V during transitionand for less than 20ns.
3. Depends on range.
Table2. Absolute MaximumRatings
(1)
Instructions for Read/Reset,Auto Select for read-
ing the Electronic Signature or Block Protection
status,Programming,Blockand ChipErase,Erase
Suspend and Resume are written to the device in
cyclesof commandstoa CommandInterfaceusing
standardmicroprocessorwrite timings.
The device is offeredin TSOP48(12 x 20mm)and
SO44packages.Both normaland reversepinouts
are availablefor the TSOP48package.
Organisation
The M29F100 is organised as 128Kb x8 or 64Kb
x16 bits selectable by the BYTE signal. When
BYTE is Low the Byte-wide x8 organisation is
selected and the address lines are DQ15A–1and
A0-A15. The Data Input/Output signal DQ15A–1
actsasaddresslineA–1which selectsthe loweror
upper Byte of the memory word for output on
DQ0-DQ7, DQ8-DQ14remainat High impedance.
When BYTEis Highthe memory usesthe address
inputs A0-A15 and the Data Input/OutputsDQ0-
DQ15.Memory control is providedby ChipEnable
E, OutputEnable G and Write EnableW inputs.
AReset/BlockTemporaryUnprotection RPtri-level
input provides a hardware reset when pulled Low,
andwhenheldHigh(atV
ID
)temporarily unprotects
blocks previously protected allowing them to be
programedanderased.EraseandProgramopera-
tions are controlled by an internal Program/Erase
Controller(P/E.C.). StatusRegisterdata output on
DQ7providesa Data Pollingsignal, and DQ6and
DQ2provideToggle signalsto indicatethe stateof
the P/E.C operations. A Ready/Busy RB output
indicatesthe completionof theinternalalgorithms.
MemoryBlocks
The devicesfeature asymmetrically blockedarchi-
tectureprovidingsystemmemory integration.Both
M29F100Tand M29F100Bdevices have an array
of 5 blocks, one Boot Block of 16 KBytes or 8
KWords, two Parameter Blocks of 8 KBytes or 4
KWords, one Main Block of 32 KBytes or 16
KWords and one Main Blocks of 64 KBytes or 32
KWords.The M29F100Thas the BootBlockat the
top of the memory address space and the
M29F100B locates the Boot Block starting at the
bottom. The memory maps are showed in Figure
3. Each block can be erased separately,any com-
bination of blocks can be specified for multi-block
eraseor the entire chipmay beerased.The Erase
operations are managed automatically by the
P/E.C. The block erase operation can be sus-
pended in order to read from or program to any
block not beingersased, and then resumed.
Block protectionprovides additional data security.
Each block can be separatelyprotected or unpro-
tectedagainst Program or Erase on programming
equipment.All previously protected blocks can be
temporarily unprotectedin the application.
Bus Operations
The following operations can be performed using
theappropriatebus cycles:Read(Array,Electronic
Signature, Block Protection Status), Write com-
mand, OutputDisable,Standby,Reset, Block Pro-
tection, Unprotection, Protection Verify,
Unprotection Verify and Block Temporary Unpro-
tection.See Tables4 and 5.
DESCRIPTION
(Cont’d)
3/30
M29F100T, M29F100B
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