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参数资料
| 型号： | MB86832-66PFV-G |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 66 MHz, RISC PROCESSOR, PQFP176 |
| 封装： | 24 X 24 MM, 0.50 MM PITCH, EIAJ, PLASTIC, SQFP-176 |
| 文件页数： | 10/54页 |
| 文件大小： | 269K |
| 代理商： | MB86832-66PFV-G |
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SPARClite Series 32-Bit RISC Embedded Processor
18
Fujitsu Microelectronics, Inc.
Bus Interface
The bus interface unit (BIU) is designed for simplicity and high
performance. Separate address and data buses make it easy to build
fast systems.At the same time, on-chip circuitry allows these systems
to be built with a minimum of external hardware.
The BIU runs at the rate of the external clock, however the CPU
and core logic can run at rates of
1, 2, 3, 4, or 5 that rate.
This is provided to ease the system design for applications where
the CPU is running at a high frequency.
The bus interface supports fully programmable wait-state
generation, address decoding with chip select outputs, booting from
8-, 16-, and 32-bit wide memory, and an auto-reload timer.
A burst mode supports fast cache line lls.Address pinsADR<3:2>
track the internal address changes during burst mode.
Each chip select can also be programmed to support 8-, 16-, or 32-
bit wide memory.An exception is when -CS4 and -CS5 are used with
the internal DRAM controller enabled, only 16- and 32-bit width is
supported for these areas. See the section on the DRAM controller
for a more detailed description of DRAM access.
Interrupt Controller
The interrupt controller (IRC) functions are a superset of the IRC
functions of the MB86930 and MB86940 devices. It has four
modes:
Trigger Mode Registers 0 and 1 set the trigger modes for each
channel of channels 8 through 15 and channels 1 through 7,
respectively.As shown inTable 6, an interrupt can be triggered by a
high level, low level, rising edge, or falling edge.
Note:
IRQx signals that do not have pins are tied low internally. If the trigger mode for
these signals is set to low level, continuous interrupts will be generated.
Table 6. Interrupt Trigger Modes
TRGMD
Trigger Mode
00
High Level (Initial Value)
01
Low Level
10
Rising Edge
11
Falling Edge
sub-
block
7
sub-
block
6
sub-
block
4
sub-
block
0
block
0
1
0
127
Tag Entry Format
User/Supervisor
lru
lock
5
6
11
address tag
0
1
2
3
127
sub-
block
5
sub-
block
3
sub-
block
2
sub-
block
1
10
31
Valid bits
BANK 1 or BANK 2
Figure 3. Data Cache Organization
Figure 4. Instruction Cache Organization
sub-
block
7
sub-
block
6
sub-
block
4
sub-
block
0
block
0
1
0
127
Tag Entry Format
User/Supervisor
lru
lock
5
6
11
address tag
0
1
2
3
127
sub-
block
5
sub-
block
3
sub-
block
2
sub-
block
1
10
31
Valid bits
BANK 1 or BANK 2
相关PDF资料 |
PDF描述 |
|---|---|
| MB86860 | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352 |
| MB86931-20ZF-G | 32-BIT, 20 MHz, RISC MICROCONTROLLER, CQFP256 |
| MB86931-40ZF-G | 32-BIT, 40 MHz, RISC MICROCONTROLLER, CQFP256 |
| MB86933H-20PF-G | 32-BIT, 20 MHz, RISC PROCESSOR, PQFP160 |
| MB86934-60ZF | 32-BIT, 60 MHz, RISC PROCESSOR, CQFP256 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MB86832-80PFV | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86833 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86833PMT2 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86834 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86834-120PFV | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
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