参数资料
型号: MB86832-66PFV-G
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 66 MHz, RISC PROCESSOR, PQFP176
封装: 24 X 24 MM, 0.50 MM PITCH, EIAJ, PLASTIC, SQFP-176
文件页数: 14/54页
文件大小: 269K
代理商: MB86832-66PFV-G
MB86832
Fujitsu Microelectronics, Inc.
21
Figure 6.
DRAM Controller Conguration
Programmable Chip Select
The core logic includes six programmable chip selects with wait-
state generator circuits. Chip select address ranges must not overlap.
Some chip selects have assigned functions, as shown in Table 9,“Use
of Chip Select,”on this page.
Chip select settings and wait state settings must be made while the
cache is disabled. If the write buffer is operating with the cache
enabled and these settings are changed, the bus interface unit may
stop operating normally. ARSR (Address Range Specier
Register), AMR (Address Mask Register), SPGMR (Same Page
Mask Register) and WSSR (Wait State Specier Register) settings
must be made during reset initialization, before enabling the
cache.
Table 9. Use of Chip Select
ADR<25:1>
-AS
RDWR
-BE<3:0>
-CS4
-SAMEPAGE
-TIMER_OVF
-DBURSTEN
Other
-READY
MPX
-RAS<3:0>
-CAS<3:0>
-DWE<3:0>
-DOE
RAS/CAS MPX
Timing Control
ADR<13:2>
CPU CORE
DRAMC
MB86832
-CS0
Boot ROM area
-CS1
General purpose
-CS2
General purpose
-CS3
Control and status registers for external peripheral control and
status registers
-CS4
DRAM area
-CS5
Denes a noncacheable region when the noncache function is
enabled and the built-in DRAM controller is enabled
DRAM Controller
High-speed page-mode DRAM support (burst mode and non-
burst mode supported)
EDO (hyperpage) mode DRAM support (burst mode use
only)
Memory bus width: 16- and 32-bit bus width supported
DRAM page size 256 to 4096 columns
Self-refresh during sleep mode support
Programmable RAS and CAS timing parameters
DRAM controller enabled by setting the DRAM controller
enable bit (bit 6) of the System Support Control Register
(SSCR)
Burst mode enabled by setting the DRAM burst enable bit
(bit 7) of the System Support Control Register
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