- 您现在的位置：买卖IC网 > PDF目录69018 > MB86832-66PFV-G 32-BIT, 66 MHz, RISC PROCESSOR, PQFP176 PDF资料下载
参数资料
| 型号： | MB86832-66PFV-G |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 66 MHz, RISC PROCESSOR, PQFP176 |
| 封装： | 24 X 24 MM, 0.50 MM PITCH, EIAJ, PLASTIC, SQFP-176 |
| 文件页数： | 25/54页 |
| 文件大小： | 269K |
| 代理商： | MB86832-66PFV-G |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页当前第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页
MB86832
Fujitsu Microelectronics, Inc.
31
Bus Operation
The bus interface unit (BIU) is the interface to external devices.
It includes the address and data buses, the interrupt request bus, and
various control signals.At any time, the BIU is either handling
transfers to or from off-chip devices, arbitrating for bus access, or
idle.
Operation of the BIU
On writes to external memory, the BIU uses a four-word write
buffer. When the BIU receives a request for a write transaction it
stores the write data and address in the write buffer, which releases
the IU to continue executing out of on-chip cache.The BIU then
proceeds to complete the write to external memory. In most cases,
the write buffer will hide external memory latency from the IU.
The exceptions are in cases where the write buffer is full from
previous transactions or if the subsequent IU cycle results in an
instruction cache or data cache read miss. In these cases, IU
execution is held until the write buffer is emptied.
The write buffer operates only when both the instruction and data
caches are enabled. When the bus is granted to an external bus
master, a store to the write buffer does not cause the assertion of
-PBREQ.This allows the external bus master to continue operating
while the CPU is executing out of the on-chip caches.
The BIU includes a one-stage prefetch buffer for instruction fetches.
This buffer is used to fetch the next sequential instruction after an
instruction cache miss.The instruction is prefetched only if the BIU
does not have a request for a bus transaction from the IU and no
external device is requesting use of the bus.The prefetch buffer
operation is suspended if the buffer is full.This occurs if the
prefetched instruction is a hit in the instruction cache.The buffer
restarts after another instruction cache miss. If an exception occurs
during an instruction prefetch, the exception is not sent to the IU
unless the instruction is actually requested by the IU.The prefetch
buffer operates only when the instruction cache is enabled.
In any cycle, the BIU can receive a request for access to either or both
instruction and data memory. If it receives a request for both in the
same cycle, it completes the data memory transaction rst.
Exception Handling
The external memory system can indicate an error during a memory
operation.The BIU signals the appropriate data or instruction
exception to the IU which calls the appropriate trap.
As mentioned above, the IU can continue operation after putting the
data and address for a store in the write buffer. If an exception is
detected while completing this buffered write, then the BIU signals a
data access exception to the IU.
Any system which needs to recover from this error should store the
address and data of these write transactions in hardware. If the
system can generate both read and write exceptions, then the system
must also provide a status bit which indicates whether the exception
was generated on a read or a write transaction. With this
information, the data access exception service routine can determine
the cause of the exception and recover.
If the write buffer is operating, an exception can potentially cause
other exceptions due to the ush of the four write buffer levels.
A system that needs the ability to recover must store up to four
separate sets of address and data.
Bus Cycles
Figure 7 on page 34 through Figure 28 on page 45 illustrate
representative combinations of bus cycles.
Load
Regardless of the external bus width (8, 16, or 32 bits), all
instruction fetches and data reads (including load byte and load half
word) load a 32-bit quantity.This is done for compatibility with
MB8693X processors with data cache where the smallest
granularity in the cache is one word. Bus width can be programmed
based on chip select areas to be 8, 16, or 32 bits.
Load (32-bit bus width)
Whenever a load from data memory is requested or an instruction
cache miss occurs, the BIU performs a read from external memory
(see Figure 7 on page 34).
With a 32-bit external data bus, a read transaction begins with the
BIU asserting –AS, to indicate a new bus transaction.The –AS
signal is de-asserted after one cycle.At the same time the
ADR<27:2> andASI<3:0> bits are driven with the location to be
read.The BIU drives the RDWR signal high to indicate a read
transaction. Because all loads transfer 32 bits, -BE<3:0> are all
driven low.
The external memory system responds with the read data on pins
D<31:0>. It also asserts the –READY signal when the external
device is ready for the bus cycle to complete. For slow memory, the
–READY signal can be delayed until data is valid.
A load double operation is treated as two back-to-back word reads.
相关PDF资料 |
PDF描述 |
|---|---|
| MB86860 | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352 |
| MB86931-20ZF-G | 32-BIT, 20 MHz, RISC MICROCONTROLLER, CQFP256 |
| MB86931-40ZF-G | 32-BIT, 40 MHz, RISC MICROCONTROLLER, CQFP256 |
| MB86933H-20PF-G | 32-BIT, 20 MHz, RISC PROCESSOR, PQFP160 |
| MB86934-60ZF | 32-BIT, 60 MHz, RISC PROCESSOR, CQFP256 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MB86832-80PFV | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86833 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86833PMT2 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86834 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86834-120PFV | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
发布紧急采购，3分钟左右您将得到回复。