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参数资料
| 型号： | MB86832-66PFV-G |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 66 MHz, RISC PROCESSOR, PQFP176 |
| 封装： | 24 X 24 MM, 0.50 MM PITCH, EIAJ, PLASTIC, SQFP-176 |
| 文件页数： | 15/54页 |
| 文件大小： | 269K |
| 代理商： | MB86832-66PFV-G |
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SPARClite Series 32-Bit RISC Embedded Processor
22
Fujitsu Microelectronics, Inc.
-CS0
The -CS0 output is a chip select for boot ROM. NoAddress Range
Specier Register exists for -CS0. It has a base address of 0.
Following reset, the CPU vectors to address 0. Unlike the other chip
select outputs, the -CS0 output defaults to an enabled condition
after reset.
-CS1 and -CS2
General-purpose chip selects with no special limitations.
-CS3
The -CS3 area is assigned to peripheral control and status registers,
and it is limited to a range of 1 Kbyte including both internal and
external registers. When on-chip peripherals are accessed, the bus
signalsADR<27:2>, -AS, RDWR, -BE<3:0>, and -RDYOUT are
driven with the same timing used for external bus cycles. Data also
appears on D<31:0> when storing to on-chip peripherals selected
with -CS3.
The -CS3 area can be set to 16- or 32-bit bus width, but 8-bit is not
available. 32-bit bus-width peripherals can be assigned to
-CS3, and when using the Wait State Specier Register, the Single
Cycle Non Burst Mode bit and the Single Cycle Burst Mode bit must
be clear. One or more wait states must be programmed, and the
Override bit must be set.These rules apply to both on-chip and off-
chip peripherals. On-chip peripherals, however, must be accessed
withADR<1:0> equal to zero using Half-Word Load and Half-
Word Store instructions, because the on-chip peripherals only use
D<15:0>.
-CS4
The -CS4 area is assigned to DRAM. When the built-in DRAM
controller is used, -CS4 is the DRAM chip select. Even if an external
DRAM controller is used, -CS4 must be assigned to DRAM, because
the page-hit detection circuit (i.e. -SAMEPAGE generator circuit) is
enabled for the -CS4 area.Whether the on-chip DRAM controller or
an external controller is used, -CS4 wait-state generation must be
disabled. In the Wait State Specier Register, the Wait Enable bit
and the Single Cycle Non Burst Mode bit must be clear.
-CS5
When a noncacheable area is not present, -CS5 can be used as a
general-purpose chip select. When both a noncachable area and the
on-chip DRAM controller are used, the -CS5 area is forced to be
noncacheable. Unlike the other chip selects, the -CS5 address range
may overlap the -CS4 area, to dene a noncacheable area in DRAM.
These areas may overlap whether or not the DRAM controller is
enabled. When -CS5 is used in a DRAM area, the
-CS5 wait state generator must be disabled. In the Wait State
Specier Register, the Wait Enable bit and the Single Cycle Non
Burst Mode bit must be clear. If the DRAM controller is enabled, the
bus width of the -CS5 area will be the same as that specied for the -
CS4 area.
Idle Cycle Insertion Function
IDLEEN Pin Tied Low
When the IDLEEN pin is tied low and a write cycle comes
immediately after a read cycle, an idle cycle is automatically inserted
for one CLKIN period.
IDLEEN Pin Tied High
When the IDLEEN pin is tied high and a bus cycle immediately
follows an access to the -CS0 area, an idle cycle is inserted for two
CLKIN periods unless the second bus cycle also accesses the -CS0
area. Because EPROM output disable time is long, this function can
eliminate a tristate buffer in some designs.A single idle cycle is
inserted when a DRAM write immediately follows a DRAM read, as
shown in Table 10,“Idle Cycle Insertion Function,”on page 23.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MB86832-80PFV | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86833 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86833PMT2 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86834 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86834-120PFV | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
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