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参数资料
| 型号： | MB86832-66PFV-G |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 66 MHz, RISC PROCESSOR, PQFP176 |
| 封装： | 24 X 24 MM, 0.50 MM PITCH, EIAJ, PLASTIC, SQFP-176 |
| 文件页数： | 9/54页 |
| 文件大小： | 269K |
| 代理商： | MB86832-66PFV-G |
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MB86832
Fujitsu Microelectronics, Inc.
17
Cache
The MB86832 has separate on-chip 2-way set-associative
instruction and data caches.This allows the user to build a high-
performance system without incurring the cost of requiring fast
external memory and the associated control logic.
The caches use a buffered writethrough mechanism. Read hits can be
satised by the caches without generating external bus cycles. Write
hits are applied to both the cached data and the image of the data in
external memory. Because writes to memory are buffered, the CPU
can continue execution from cache without pausing to allow writes
to external memory to complete.The caches are physically mapped.
The data cache is organized as two banks of 128 lines (see Figure 3
on page 18 for the organization of one bank).The instruction cache
is organized as two banks of 128 lines (see Figure 4 on page 18 for
the organization of one bank).
Lines are divided into sub-blocks each four bytes wide. On a cache
miss, the caches are updated either 1 word (4 bytes) at a time, or 4
words at a time using the processor’s burst mode feature. Single-
word updates minimize interrupt latency associated with long cache
line replacements, while 4-word burst rells maximize the use of
available bus bandwidth.An instruction pre-fetch buffer fetches the
next sequential instruction anticipating that it will be needed to
satisfy the next instruction cache miss.
The caches can be used in either normal mode or one of two lock
modes.The two lock modes allow either the entire cache or just
selected cache lines to be locked.The lock modes allow time-critical
or performance-sensitive instructions and data to be locked in cache.
Global locking affects the entire content of either the instruction or
data cache.Two control bits in the Cache/BIU Control Register
enable or disable locking for either cache. With the entire cache
locked, no valid cache line can be kicked out of the cache.To insure
best performance however, invalid lines are allocated if possible.This
is done automatically and incurs no time penalty.
Local cache locking makes it possible to dynamically lock selected
instructions or data in the appropriate cache.This feature provides
the exibility, for example, to implement a known, deterministic
response for certain critical interrupt routines by locking the
routine’s code and data into the cache. Cache lines can also be locked
to give priority to often used instructions or data which might
otherwise be removed from cache.
In local lock mode, each entry can either be locked individually by
software or automatically with hardware assist. For individual
locking, software writes the lock bit in the appropriate cache tag
line. For automatic locking, a bit in each Lock Control Register
enables or disables the feature.The enable bit is set at the beginning
of a routine for which the entries are to be locked.This causes the
location of any cache access occurring while the bit is enabled to be
locked into the cache. In addition to requiring just one initial cycle
to enable, automatic entry locking incurs no overhead while in
effect. Locked locations can be cleared with a single write to a
control register.
In unlocked operation, the data cache uses a write-through update
policy and allocates a cache line only on a load. Writes are buffered
so that the processor can continue executing while data is written
back to memory. In contrast, writes to locked data cache locations
are not written through to main memory. Besides reducing external
bus activity, this effectively congures a portion of data cache as on-
chip RAM which does not map to external memory.
The data and instruction caches are designed to be accessed
independently over separate data and instruction buses to allow data
to be loaded from and stored to the cache at peak rates of 1 per
instruction.
Different data memory spaces can be congured as cacheable or non-
cacheable through either software programming or hardware
control.
Following reset, bit 7 of Cache/BIU Control Register (ASI=0x01
ADR=0x0000 0000) is initialized so that cacheability is controlled
by a hardware pin, -NONCACHE. When the
-NONCACHE pin is low, the data associated with the address is non-
cacheable, otherwise it is cacheable. In this mode, the hardware
control of cacheability is independent of the chip selects.
The user can set bit 7 of Cache/BIU Control Register to allow
software to control cacheability. By programming a few bits in the
Bus Width and Cacheable Register (ASI = 0x01, address = 0x0000
016C), cacheability can be controlled by which chip select is used.
Cacheability for the -CS4 and -CS5 chip selects are special cases.
When the internal DRAM controller is disabled, the cacheability of
-CS4 and -CS5 is the same as the other chip selects. When the
internal DRAM controller is enabled, the data memory space
selected by -CS4 is cacheable, and the data memory space referred by
-CS5 is non-cacheable. Unlike the other chip selects, -CS5 can be
programmed to overlap the -CS4 address range to dene a
noncachable region within DRAM.
相关PDF资料 |
PDF描述 |
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| MB86860 | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352 |
| MB86931-20ZF-G | 32-BIT, 20 MHz, RISC MICROCONTROLLER, CQFP256 |
| MB86931-40ZF-G | 32-BIT, 40 MHz, RISC MICROCONTROLLER, CQFP256 |
| MB86933H-20PF-G | 32-BIT, 20 MHz, RISC PROCESSOR, PQFP160 |
| MB86934-60ZF | 32-BIT, 60 MHz, RISC PROCESSOR, CQFP256 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MB86832-80PFV | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86833 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86833PMT2 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86834 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86834-120PFV | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
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