参数资料
型号: MB86832-66PFV-G
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 66 MHz, RISC PROCESSOR, PQFP176
封装: 24 X 24 MM, 0.50 MM PITCH, EIAJ, PLASTIC, SQFP-176
文件页数: 4/54页
文件大小: 269K
代理商: MB86832-66PFV-G
SPARClite Series 32-Bit RISC Embedded Processor
12
Fujitsu Microelectronics, Inc.
Table 4. Pin Status Description
Access Type
Pin
During Reset
During Bus Grant
ADR <27:2>
O(X)
I(D)
-
AS
O(H)
I(Z)
-
BE0
O(X)
O(Z)
-
BE1
O(X)
O(Z)
-
BE2/ADR1
O(X)
O(Z), I(Z)
-
BE3/ADR0
O(X)
O(Z)
-
CS<5:0>
O(H)
I(Z), O(Z)
-
ERROR
O(H)
O(V)
-
LOCK
O(H)
O(Z)
-
PDOWN
O(H)
-
PBREQ
O(H)
O(V)
-
SAMEPAGE
O(H)
O(V)
D<31:0>
I(Z)
RDWR
O(H)
I(Z)
-
BGRNT
O(H)
O(L)
ASI<3:0>
O(X)
I(Z)
-
RDYOUT
O(V)
-BMREQ
O(H)
-TIMER_OVF
O(H)
O(V)
-
RAS<3:0>
O(H)
O(V)
-
CAS<3:0>
O(H)
O(V)
-
DOE
O(H)
O(V)
:
Output driven to a valid level.
O(X)
:
Output is undened.
O(Z)
:
Output is in high impedance.
O(H)
:
Output is driven high.
O(L)
:
Output is driven low.
I(Z)
:
Input is high impedance.
I(D)
:
If the DRAM controller is enabled, the address sampled
on the assertion of -AS will be driven from the next
clock until -READY is asserted. If the address maps to a
DRAM area, a multiplexed address will be driven. If the
DRAM controller is disabled, the signal will be in high
impedance.
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