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参数资料
| 型号： | MB86832-66PFV-G |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 66 MHz, RISC PROCESSOR, PQFP176 |
| 封装： | 24 X 24 MM, 0.50 MM PITCH, EIAJ, PLASTIC, SQFP-176 |
| 文件页数： | 7/54页 |
| 文件大小： | 269K |
| 代理商： | MB86832-66PFV-G |
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MB86832
Fujitsu Microelectronics, Inc.
15
Figure 1.
MB86832 Integer Unit Data Path
A ve-stage instruction pipeline decodes the instructions and
generates the control signals to the other blocks.The pipeline
consists of Fetch (F), Decode (D), Execute (E), Memory (M),
and Writeback (W) stages. Instruction memory is addressed and
instructions are returned in the (F) stage, the register le is
addressed and operands are returned in the (D) stage, theALU
produces results in the (E) stage, external memory is addressed in the
(M) stage, and the register le is written back in the (W) stage.
Address Space
The MB86832 offers multiple large address spaces including separate
user and supervisor spaces. In addition to 26 address lines, 8 alternate
address space identier bits (ASIs) distinguish between protected and
unprotected space. Of the 256 possibleASI values, two select user
instruction and data spaces, while the remainingASI values dene
supervisor spaces. Included in the latter are peripheral control
registers and direct access to the cache tag and data memories.
Registers
The MB86832 integer unit register set consists of both general-
purpose registers and dedicated registers used for control and status.
The 136 general-purpose registers are divided into 8 global
registers and 8 overlapping blocks or“windows”. Each window
contains 24 registers. Of these, 8 are local to the window, 8“out”
registers overlap with the next window, and 8“in”registers overlap
with the previous window (see Figure 2 on page 16).
This organization makes it easy to pass parameters to subroutines.
Parameters are written to the“out”registers and the subsequent
procedure call decrements the window pointer to make a new set of
registers available.The passed parameters are now available to the
subroutine in the current window’s“in”registers.
ir
e_ir
m_ir
w_ir
INSTRUCTION
BLOCK
adder
pc
0
TBR
inc (+4)
d_pc
e_pc
m_pc
ADDRESS
BLOCK
B
A
ALU / SHIFTER
PSR/WIM/Y
st_align
ld_align
read 1
read 2
read 3
write
REGISTER FILE
EXECUTE
BLOCK
I DATA
D ADDRESS
D DATA
R Register
I ADDRESS
CPU
The MB86832 core is a high-performance, fully custom
implementation of the SPARC architecture.The core is compact to
leave chip real estate available for peripheral integration.The
modular architecture allows the device family to be customized for
varying application requirements.The core is made up of three
functional units: the Instruction block, theAddress block and the
Execute block. (see Figure 1 below)
When a reset or trap occurs, the processor enters supervisor mode.
In this mode, instructions and data come from supervisor space.
While in supervisor mode, the processor has access to all protected
ASI spaces. FourASI spaces have been reserved for application-
dened data spaces.
The distinction between user and supervisor space allows the
hardware to protect against program errors. In developing real-time
applications, for example, the separate spaces provide a mechanism
for protecting the operating system from bugs in application code.
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| MB86931-40ZF-G | 32-BIT, 40 MHz, RISC MICROCONTROLLER, CQFP256 |
| MB86933H-20PF-G | 32-BIT, 20 MHz, RISC PROCESSOR, PQFP160 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MB86832-80PFV | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86833 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86833PMT2 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86834 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86834-120PFV | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
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