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参数资料
| 型号： | MB86832-66PFV-G |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 66 MHz, RISC PROCESSOR, PQFP176 |
| 封装： | 24 X 24 MM, 0.50 MM PITCH, EIAJ, PLASTIC, SQFP-176 |
| 文件页数： | 3/54页 |
| 文件大小： | 269K |
| 代理商： | MB86832-66PFV-G |
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MB86832
Fujitsu Microelectronics, Inc.
11
Note:
In the signal descriptions, names preceded by a minus sign (–) indicate active low assertion. Dual function pins have two names separated by a slash (/).
-BMREQ
O
BURST MODE REQUEST: This signal is asserted by the processor to indicate to the external system that the processor’s burst mode is enabled
in the Bus Control Register (BCR) and the current transaction can be a burst. If the external system supports burst mode, –BMACK can be asserted
concurrently with –READY to begin the burst mode transfer. -BMREQ is asserted even when the DRAM burst enable bit in the System Support
Control Register (SSCR) is set. However, in this case the internal DRAM controller drives the signal, so it is not necessary for external logic to
drive -BMREQ.
-BMACK
I
BURST MODE ACKNOWLEDGE: This signal is asserted by external logic to indicate that it can support burst mode for the address
currently on the bus. If driven low on or before the clock on which -READY is asserted, burst mode data transfer is used. The signal can be driven
low in the same clock as -READY, or a clock before that and sustained until -READY is driven. If the DRAM burst enable bit of the
System Support Control Register (SSCR) is set, burst mode is used even if -BMACK is not asserted.
-SAME
PAGE
O
SAME PAGE DETECT: When bit 5 of the System Support Control Register (SSCR) is set, RAS page-hit detection is enabled. The address in the
Same Page Master Register (SPSMR) and the previously accessed address are compared, and if they match -SAMEPAGE is asserted.
–SAMEPAGE is never asserted in the rst bus cycle following a transfer of bus control. The page size is specied in the Same Page Mask Register.
-RAS0
-RAS1
-RAS2
-RAS3
O
DRAM ROW ADDRESS STROBE: These are the row-address strobes from the DRAM controller.
-CAS0
-CAS1
-CAS2
-CAS3
O
DRAM COLUMN ADDRESS STROBE: These are the column address strobes from the DRAM controller. When 32-bit bus width is selected
and 2-CAS DRAM conguration is used, -CAS<0:3> correspond to byte 0 (b31-b24), byte 1 (b23-b16), byte 2 (b15-b8) and byte 3 (b7-b0). With
16-bit bus width and 2-CAS DRAM, -CAS2 and -CAS3 correspond to byte 0 (even byte address) and byte 1 (odd byte address), respectively. -
CAS0 and -CAS1 are undened when 16-bit bus width is selected. When 2-WE DRAM is used, -CAS<0:3> are driven with identical signals.
-DWE0
-DWE1
-DWE2
-DWE3
O
DRAM WRITE ENABLE: These are the DRAM write enables. When a 2-WE DRAM conguration is used, -DWE<0:3> correspond respectively to
byte 0 (b31-b24), byte 1 (b23-b16), byte 2 (b15-b8) and byte 3 (b7-b0). When a 2-CAS DRAM is used, -DWE<0:3> are driven with identical sig-
nals.
-DOE
O
DRAM OUTPUT ENABLE: This is the output enable from the DRAM controller. DRAM interface is possible without using this signal for control
of -DWE0 and -CAS<3:0> in early-write timing when a page-mode DRAM is used, but it is required for controlling the DRAM output drivers when
EDO (hyper page-mode) is used.
-TIMER_OVF
O
TIMER OVERFLOW: When the DRAM refresh timer is enabled in the System Support Control Register (SSCR), transparent DRAM refresh can
be set up. The period between refresh cycles is programmed in the DRAM Refresh Timer Preload Register, and the signal pulse widths are pro-
grammed in the DRAM Refresh Timer Register. -TIMER_OVF is pulsed low when the timer counts down to zero. The timer is clocked by CLKIN,
without frequency multiplication. Bit 31 of the DRAM Refresh Timer Preload Register controls the pulse width, either one clock or three clocks
long. When a three-clock pulse width is selected, -TIMER_OVF can be connected to an interrupt input (IRQx) of the interrupt controller.
EMU_SD
<3:0>
I/O
EMULATOR STATUS/DATA BITS: Bidirectional pins used by a hardware emulator to control and monitor processor execution. These pins
should be left unconnected.
EMU_D <3:0>
I/O
EMULATOR DATA BITS: Bidirectional pins used by a hardware emulator to control and monitor processor execution. These pins should be left
unconnected.
–EMU_BRK
I
EMULATOR BREAK REQUEST LINE: Input used by a hardware emulator to request a trap when emulation is enabled. This pin should be left
unconnected.
–EMU_ENB
I/O
EMULATOR ENABLE: Tied low while the processor is being reset to enable hardware emulator mode on the chip. This pin should be left uncon-
nected.
Table 3. Signal Descriptions (Continued)
Symbol
Type
Description
相关PDF资料 |
PDF描述 |
|---|---|
| MB86860 | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352 |
| MB86931-20ZF-G | 32-BIT, 20 MHz, RISC MICROCONTROLLER, CQFP256 |
| MB86931-40ZF-G | 32-BIT, 40 MHz, RISC MICROCONTROLLER, CQFP256 |
| MB86933H-20PF-G | 32-BIT, 20 MHz, RISC PROCESSOR, PQFP160 |
| MB86934-60ZF | 32-BIT, 60 MHz, RISC PROCESSOR, CQFP256 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MB86832-80PFV | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86833 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86833PMT2 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86834 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86834-120PFV | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
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