- 您现在的位置：买卖IC网 > PDF目录69018 > MB86832-66PFV-G 32-BIT, 66 MHz, RISC PROCESSOR, PQFP176 PDF资料下载
参数资料
| 型号： | MB86832-66PFV-G |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 66 MHz, RISC PROCESSOR, PQFP176 |
| 封装： | 24 X 24 MM, 0.50 MM PITCH, EIAJ, PLASTIC, SQFP-176 |
| 文件页数： | 27/54页 |
| 文件大小： | 269K |
| 代理商： | MB86832-66PFV-G |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页当前第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页
MB86832
Fujitsu Microelectronics, Inc.
33
8- and 16-Bit Bus Modes
Any chip select (-CS<5:0>) can be mapped to 8-, 16-, or 32-bit bus
width, however -CS4 and -CS5 cannot be mapped to 8-bit bus
width if the DRAM controller is enabled. Memory width for -CS0 is
selected at system reset with the -BMODE8 and -BMODE16
signals. Table 13, also below, shows the bus width options available
for the -CS0 area. Memory width for the -CS<5:1> areas is
programmed by two bits for each chip select in the Bus Width and
Cacheable Register. Table 14, also below, shows the programming
bits and the corresponding bus width of each chip select.
Table 13. Bus Width Control of -CS0
Table 14. Bus Width Control Bits of -CS1 to -CS5
8- and 16-bit transactions are similar to 32-bit transactions except
that –AS is asserted only once at the beginning of the bus cycle for a
load operation, and –READY is asserted at the end of each byte or
halfword transfer.The –BE<3:0> signals indicate the byte or
halfword being read or written (see Figure 15 on page 39 through
Figure 18 on page 40).
For 32-bit writes to 8- or 16-bit memory and 16-bit writes to 8-bit
memory, the BIU drives -BE<2:3> asADR<1:0>, and initiates
multiple transactions.
When the internal DRAM controller is enabled, 8-, 16-, and 32-bit
bus width are available for -CS0 through -CS3, and only 16- or 32-
bit memory bus are available for -CS4 and -CS5, depending on the
DRAM bus width.
Burst Mode Transactions
For systems that can support burst mode transactions, the DRAM
controller can be programmed to support four-word bursts.
When burst mode is enabled, –BMREQ is asserted at the beginning
of each bus cycle for which a burst transfer is allowed (see
Table 15, also below,). If the memory system can support a burst for
the current bus address, the memory system asserts
–BMACK to begin the burst transaction. –BMACK is asserted on
the rst word of the burst transaction only. –READY is asserted for
each word of the burst. Systems that do not support burst mode for
the current address should not assert –BMACK. If either –BMREQ
or -BMACK is not asserted for a transaction, only one word is
transferred for each assertion of -AS.
Table 15. ADR<3:2> Sequence in Burst Mode
Selection of Hyperpage Mode (EDO Mode)
By setting bit 8 of the DRAM Bank Conguration Register,
hyperpage DRAM can be connected and controlled. However, if the
DRAM Burst Enable Bit (bit 7 of the System Support Control
Register) is clear, access timing is controlled in the same cycle as
normal page-mode DRAM.
When the DRAM Burst Enable Bit is set and hyperpage is enabled,
hyperpage burst access is performed. In this case,ADR<3:2> is not
a value from the CPU but is generated by the DRAM controller
itself. Because data is driven before it is received from the DRAM,
the CAS cycle time can be shortened compared to the normal page
mode burst transactions.
-BMODE16
-BMODE8
Bus Width
0
Illegal
0
1
16-bit Bus
1
0
8-bit Bus
1
32-bit Bus
BW1
BW0
Bus Width
0
32-bit Bus
0
1
8-bit Bus
1
0
16-bit Bus
1
Illegal
Bus Cycle 1
Bus Cycle 2
Bus Cycle 3
Bus Cycle 4
00
01
10
11
01
00
11
10
11
00
01
11
10
01
00
相关PDF资料 |
PDF描述 |
|---|---|
| MB86860 | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352 |
| MB86931-20ZF-G | 32-BIT, 20 MHz, RISC MICROCONTROLLER, CQFP256 |
| MB86931-40ZF-G | 32-BIT, 40 MHz, RISC MICROCONTROLLER, CQFP256 |
| MB86933H-20PF-G | 32-BIT, 20 MHz, RISC PROCESSOR, PQFP160 |
| MB86934-60ZF | 32-BIT, 60 MHz, RISC PROCESSOR, CQFP256 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MB86832-80PFV | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86833 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86833PMT2 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86834 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86834-120PFV | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
发布紧急采购，3分钟左右您将得到回复。