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| 型号： | MB86832-66PFV-G |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 66 MHz, RISC PROCESSOR, PQFP176 |
| 封装： | 24 X 24 MM, 0.50 MM PITCH, EIAJ, PLASTIC, SQFP-176 |
| 文件页数： | 2/54页 |
| 文件大小： | 269K |
| 代理商： | MB86832-66PFV-G |
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SPARClite Series 32-Bit RISC Embedded Processor
10
Fujitsu Microelectronics, Inc.
-RDYOUT
O
READY OUTPUT: Assertions of the -READY signal generated by any source, including the internal wait state generator, are visible to external
devices on this pin. Internally generated -READY assertions are synchronized to the clock. Externally generated -READY assertions will appear on
this signal with a small amount of propagation delay.
IRQ15/IRL3
IRQ14/IRL2
IRQ13/IRL1
IRQ12/IRL0
IRQ11
IRQ10
IRQ9
IRQ8
I
INTERRUPT REQUEST/INTERRUPT REQUEST LEVEL: These are interrupt inputs. Four of the inputs have a dual function. When the inter-
rupt controller (IRC) is disabled (i.e. bits 0 and 1 in the IRC Mode Register are clear), IRL<3:0> is the encoded priority level of external interrupt
requests, which compete with the on-chip interrupt sources for service by the CPU. Typically, IRL<3:0> would be generated by an external inter-
rupt controller. Higher values have greater priority. IRL=0000(2) indicates no interrupt requests are pending, and IRL=1111(2) is dened by the
SPARC architecture as a non-maskable interrupt. The external interrupt requests are sampled on two successive CLKIN clock periods to prevent
false interrupts.
When the interrupt controller is enabled, these pins are unencoded interrupt requests IRQ<15:8>. Each interrupt request can be programmed to be
triggered on a high level, low level, rising edge, or falling edge. When an interrupt signal meets the qualications to invoke an interrupt, an inter-
rupt request is loaded in the IRC Request Sense Register. The IRC performs priority resolution and encoding to generate IRL<3:0>, which is
passed to the CPU core.
-BREQ
I
BUS REQUEST: When this signal is asserted by an external bus master, the CPU releases control of the bus after the current bus operation is
completed. Certain operations require more than one bus cycle:
(1)
When an atomic load-store instruction is executed, the bus is released upon completion of both the load and the store.
(2)
In the case of a double word load or store, the bus is released if -BREQ is asserted during the transfer of word 1 after the rst word has been
transferred, and if -BREQ is asserted during the transfer of word 2, the bus is released after transferring the second word.
(3)
Store in 8- and 16-bit bus widths:
The bus is released after transmission of the entire data object (for example, when a 32-bit word is transferred with 8-bit bus size, four 8-bit
bus cycles occur before the bus is released).
(4)
Load in 8 and 16-bit bus width:
The bus is released after the entire word has been transferred.
-BGRNT
O
BUS GRANT: This signal is asserted following a bus request (i.e. -BREQ assertion) to indicate that control of the bus has been released to an
external device.
-PBREQ
O
PROCESSOR BUS REQUEST: This signal is asserted by the processor to indicate to an external bus arbiter that the CPU wants to regain con-
trol of the bus. This provides a handshake between the arbiter and the processor to allow the bus to be allocated based on demand.
-LOCK
O
BUS LOCK: The CPU asserts this signal during execution of an atomic load-store. It indicates that the current bus transaction requires more than
one bus cycle which cannot be split by releasing the bus to another bus master.
-MEXC
I
MEMORY EXCEPTION: If this signal is low on the same clock that -READY is asserted, the bus cycle is handled like a page fault, i.e. an instruc-
tion or data access exception is invoked. This signal must not be asserted except on the same clock as -READY. If a memory exception is signalled
when the ET bit of the PSR is clear (i.e. traps are disabled), the CPU enters error mode.
-ERROR
O
ERROR SIGNAL: This signal indicates that a trap has occurred while traps were disabled. When this happens, the CPU saves the PC and nPC to
a register, loads the trap type in the TBR, and goes into error mode. Error mode can only be exited by a reset.
IDLEEN
I
IDLE ENABLE: When this pin is high and the previous cycle was loaded or stored to the -CS0 area, the next cycle is started after insertion of a
two-clock idle cycle. This is intended to accommodate EPROM boot memory with slow output disable, saving the addition of a buffer chip. When
this pin is low, and a write cycle immediately follows a read cycle, an address cycle is inserted for one clock only (compatible with former versions
of SPARClite).
-BMODE8
-BMODE16
I
BOOT MODE8 and BOOT MODE16: These signals select the bus width of the -CS0 area. They are sampled during reset initialization. When -
BMODE8 is low, 8-bit bus width is selected, and when -BMODE16 is low, 16-bit bus width is selected. When both pins are tied high, the bus
width is 32 bits. The bus width of the -CS1 through -CS5 areas are not affected by these signals. The -CS1 through -CS5 areas are programmed
through the Bus Width/Cacheable Control Register BWCR. Do not tie both of these inputs low.
-NONCACHE
I
NON-CACHEABLE: This signal is asserted by external logic to indicate the data on the bus is non-cacheable. Low indicates non-cacheable and
high indicates cacheable. This signal is used when the CBIR (Cache/BIU Control Register) Cacheability Enable bit (bit 7) is set. Normally, the -
NONCACHE signal is driven on a clock in which address strobe is asserted. However, if -NONCACHE must be one clock or more late, it can be
used by setting the Cache/BIU Control Register (CBIR) Noncacheable Wait State bits (bits 9,8). This signal is ignored during instruction fetches
and when the internal cacheability is used.
-PDOWN
O
POWER DOWN: This signal indicates transition to sleep mode (i.e. low power consumption mode) when it is low.
-WKUP
I
WAKE-UP: This pin is driven low to break the CPU out of sleep mode. This pin is an asynchronous input, and must be driven with a pulse of 2 or
more CLKIN periods. This pin must only be driven low when -PDOWN is low, otherwise the behavior of the processor is undened.
-FLOAT
I
FLOAT: Driving this input low causes all output pins and bidirectional pins to go into high-impedance mode.
Table 3. Signal Descriptions (Continued)
Symbol
Type
Description
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MB86832-80PFV | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86833 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86833PMT2 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86834 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86834-120PFV | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
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