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参数资料
| 型号： | MB89PV950CF |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, 5 MHz, MICROCONTROLLER, CQFP64 |
| 封装： | 0.80 MM PITCH, PIGGY BACK, MQFP-64 |
| 文件页数： | 103/110页 |
| 文件大小： | 619K |
| 代理商： | MB89PV950CF |
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OPERATION
3– 6
3.3
Interrupt
If the interrupt controller and CPU are ready to accept interrupts when an interrupt request is received from
the internal peripherals or an external-interrupt, the CPU finished the currently-executing instruction and
executes the interrupt-processing program. Fig. 3.4 shows the interrupt-processing flowchart.
Fig. 3.4 Interrupt-processing Flowchart
All interrupts are disabled right after reset. Therefore, the main program (1) should initialize interrupts .
Each peripheral generating interrupts and the interrupt-level-setting registers (ILR1 to ILR3) in the interrupt
controller corresponding to these interrupts should be initialized. The levels of all interrupts can be set by
the interrupt-level-setting registers (ILR1 to ILR3) from address 007CH to 007EH in the interrupt controller.
The interrupt level can be set from 1 to 3, where 1 indicates the highest level, and 2 the second highest
level. Level 3 indicates that no interrupt occurs. The interrupt request of this level cannot be accepted. After
setting the peripherals, the main program executes various controls (2). Interrupts are generated from the
peripherals (3). The highest-priority interrupt requests are identified from those occurring at the same time
by the interrupt controller and are transferred to the CPU. The CPU then checks the current interrupt level
and the status of the I-flag (4), and starts the interrupt processing.
The CPU performs the interrupt processing to save the contents of the current PC and PS in the stack (5)
and fetches the entry addresses of the interrupt program from the interrupt vectors. After updating the IL
value in the PS to the required one, the CPU starts executing the interrupt-processing routine.
Clear the interrupt sources (6) and process the interrupts in the user’s interrupt-processing routine. Finally,
the CPU restores the PC and PS values from the stack (8) by the RETI instruction; and then return to the
interrupted instruction.
Note: Unlike the F2MC-8 family, A and T are not saved in the stack at the interrupt time.
Internal bus
Register file
IPLA
IR
PS
I
IL
Check
Comparator
MB89600 CPU
(4)
RAM
(8)
(5)
Enable FF
Source FF
Main program
Reset clear
(1) Initialize
interrupt.
(2) Main program
execution
(8)
PC, PS restored
Restore PC, PS.
(7) Interrupt
processing
IL updated
(5)
PC, PS saved
(3)
Interrupt
generation
(4)
Level
decided
(6) Clear request.
AND
Level
comparator
Interrupt controller
(1)
(3)
(6)
Peripheral
(4)
Interrupt
processing
RETI
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