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参数资料
| 型号： | MB89PV950CF |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, 5 MHz, MICROCONTROLLER, CQFP64 |
| 封装： | 0.80 MM PITCH, PIGGY BACK, MQFP-64 |
| 文件页数： | 39/110页 |
| 文件大小： | 619K |
| 代理商： | MB89PV950CF |
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HARDWARE CONFIGURATION
2– 19
(3) Description of functions
The function of each port is described below.
P00 to P07:
N-ch open-drain type input/output ports
(also used as segment output)
P10 to P17:
N-ch open-drain type input/output ports
(also used as segment output)
P20 to P25:
N-ch open-drain type input/output ports
(also used as segment output)
Operation for output port
The value written at the PDR is output to the pin. When the PDR is read,
usually, the value of the pin is read instead of the contents of the output
latch. However, when the Read Modify Write instruction is executed, the
contents of the output latch are read. Therefore, the bit-processing
instruction can be used even if input and output are mixed with each other.
Operation for input port
When using these ports as input ports, set 1 at the PDR and turn the
output transistor off. The value of the pin can always be read when the
PDR is read. When the segment output is selected by the LCD controller
port/segment select bit, the input data is always read as 0.
Operation for segment output
When using these ports as segment outputs, the segment output must
be selected by the mask option. When segment output is selected using
the LCD controller port/segment select bit, these ports can be used as
segment outputs.
State at reset
At reset, these ports serve as port inputs. The PDR is initialized to 1 and
the output transistor is turned off at all bits.
State in stop mode
For segment output, the output state when the CPU enters the stop mode
is held. For port output, the pins states in stop mode are controlled by
SPL bit in standby control register (STBC).
When SPL=0, pin states before entering stop mode are held.
When SPL=1, port pins go high impedance in stop mode.
Peripherals
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