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参数资料
| 型号： | MB89PV950CF |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, 5 MHz, MICROCONTROLLER, CQFP64 |
| 封装： | 0.80 MM PITCH, PIGGY BACK, MQFP-64 |
| 文件页数： | 76/110页 |
| 文件大小： | 619K |
| 代理商： | MB89PV950CF |
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HARDWARE CONFIGURATION
2– 53
(4) Description of operation
The operation of 8-bit serial I/O is described below.
(a) Outline
This module consists of the serial-mode register (SMR) and serial-data
register (SDR). At serial output, data in the SDR is output in bit serial to
the serial output pin (SO) in synchronization with the falling edge of a serial
shift-clock pulse generated from the internal or external clock. At serial
input, data is input in bit serial from the serial input pin (SI) to the SDR at
the rising edge of a serial shift-clock pulse.
(b) Operation modes
The serial I/O has three internal shift-clock modes and one external shift-
clock mode according to the type of shift-clock, which are specified by the
SMR. Mode switching or clock selection should be made with serial I/O
stopped (SST bit of SMR = 0).
a. Internal shift-clock mode
Operation is performed by the internal clock. A shift-clock pulse with a
duty of 50% is output at the SCK pin as a synchronous timing output.
Data is transferred bit-by-bit at every clock pulse.
b. External shift-clock mode
Data is transferred bit-by-bit at every clock pulse in synchronization with
the external shift-clock pulse input from the SCK pin. The transfer speed
can be from DC to 1 (2 instruction cycles). When one instruction cycle
is 1
s (at 5 MHz oscillation), the transfer speed can be up to 500 kHz.
Do not write data to the SMR and SDR during the serial I/O operation in
either mode.
Peripherals
#0 #1 #2
#5 #6 #7
#0 #1 #2
#5 #6 #7
#7
#6
#5
#4
#3
#2
#1
#0
#7
#6
#5
#4
#3
#2
#1
#0
SDR
SO
SI
CK
0
Shift-clock pulse
P
S conversion
S
P conversion
Serial output
Serial input
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