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参数资料
| 型号： | MB89PV950CF |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, 5 MHz, MICROCONTROLLER, CQFP64 |
| 封装： | 0.80 MM PITCH, PIGGY BACK, MQFP-64 |
| 文件页数： | 41/110页 |
| 文件大小： | 619K |
| 代理商： | MB89PV950CF |
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HARDWARE CONFIGURATION
2– 21
P30, P31:
N-ch open-drain output, CMOS input
P32, P33:
N-ch open-drain type input/output ports
(also used as LCD controller power supply V1,V2)
Operation for output port
The value written at the PDR is output to the pin. When the PDR is read,
usually, the value of the pin is read instead of the contents of the output
latch. However, when the Read Modify Write instruction is executed, the
contents of the output latch are read. Therefore, the bit-processing
instruction can be used even if input and output are mixed with each other.
Operation for input port
When using these ports as input ports, set 1 at the PDR and turn the
output transistor off. The value of the pin can always be read when the
PDR is read. When V1/V2 is selected by PSEL bit of LCDR, the input
data is always read as 0.
Operation for V1 and V2
The PSEL bit in LCDR (see page 2-60) must be cleared in order to choose
P32/P33 as LCD controller power supply.
State at reset
At reset, these ports serve as LCD controller power supply. The PDR is
initialized to 1 and the output transistor is turned off at all bits. Since PSEL
bit of LCDR will be reset to zero (see page 2-60), therefore P32/P33 will
be configured to V1/V2 right after reset.
State in stop mode
If P32/P33 is chosen as V1/V2 and stop mode is triggered, the voltage
at those pins before stop mode will be held. For port output, the pins
states in stop mode are controlled by SPL bit in standby control register
(STBC).
When SPL=0, pin states before entering stop mode are held.
When SPL=1, port pins go high impedance in stop mode.
Peripherals
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