参数资料
型号: MB89PV950CF
元件分类: 微控制器/微处理器
英文描述: 8-BIT, 5 MHz, MICROCONTROLLER, CQFP64
封装: 0.80 MM PITCH, PIGGY BACK, MQFP-64
文件页数: 7/110页
文件大小: 619K
代理商: MB89PV950CF
MASK OPTIONS
5– 3
Table 5–1 Mask Options
No.
Model
MB89953
MB89P95x
MB89PV950
Specification method
Select when ordering
mask
Set by EPROM
Fixed
1
Port pull-up resistor
P40 to P46
Can be selected for each
pin
Can be selected for
each pin
No pull up resistor
2
Port/Segment output
P00 toP07, P10toP17,
P20 to P25
Can be selected for
every 8 to 1 pins*2
Port/Segment
output *3
Port/Segment
output *3
3
Power-on reset
Power-on reset available
Power-on reset unavailable
Can be selected
Power-on reset
available
4
Selection of main clock oscil-
lation stabilization time
(at 5 MHz)*1
About 218 /fch (about 52.4 ms)
About 214 /fch (about 3.28 ms)
Can be selected
218/fch
5
Reset pin output
Reset output available
Reset output unavailable
Can be selected
Reset output available
*1 The main clock oscillation stabilization time is generated by dividing the main clock oscillation. Since
the oscillation cycle is unstable immediately after oscillation starts, the time in this table is only a guide.
*2 Port/segment output switching should be specified in the same manner as the port allocation set by
the segment output select register in the LCD controller described on page 2-61.
*3 When those pins are used as ports, applied voltage should never be higher than V3.
Table 5–2 Recommended port/segment mask option combinations
Number of
segments
Number of
I/O ports *1
Mask Options
P00/SEG20
to
P07/SEG27
P10/SEG28
to
P13/SEG31
P14/SEG32
to
P15/SEG33
P16/SEG34 P17/SEG35
P20/SEG36
to
P23/SEG39
P24/SEG40
to
P25/SEG41
42
11
XXXXX
XX
41
12
XXXX
O
X
40
13
XXX
O
XX
38
15
XX
O
XX
34
19
X
OOOO
X
26
27
O
OOOO
X
40
13
XXXXX
X
O
22
31
O
OOOO
O
X
20
33
O
OOOO
OO
X = Mask option is selected for LCD segment outputs
O = Mask option is selected for port outputs
*1 This column of numbers assume that all the multiplexed peripherals are disabled.
If any customer want to choose the mask option combination which is not shown in Table 5–2, please
inform Fujitsu for special testing arrangement.
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