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| 型号： | MB89PV950CF |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, 5 MHz, MICROCONTROLLER, CQFP64 |
| 封装： | 0.80 MM PITCH, PIGGY BACK, MQFP-64 |
| 文件页数： | 50/110页 |
| 文件大小： | 619K |
| 代理商： | MB89PV950CF |
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HARDWARE CONFIGURATION
2– 29
(b) PWM operation
Setting the P/TX bit of the CNTR to 1 gives the PWM operation mode. The
COMR specifies the duty of the output pulse. Pulses can be output with
1/256 resolution and a duty of 0% to 99.6%.
When 0 (00
H) is written at the COMR, the duty of the PWM output pulse is
0%; when 128 (80
H) is written, the duty is 50%, and when 255 (FFH) is
written, it is 99.6%.
The value of COMR is transferred to the comparator latch when the value
of the counter is 00
H. If the value of the COMR is rewritten in the PWM
operation mode, it becomes effective from the next cycle.
At starting (counter = 00), output is high. When the counter matches the
compare register, output goes low.
Fig. 2.12 PWM Pulse Output
In the PWM operation mode, the values at the TIR bit of the CNTR have
no meaning. No interruption occurs even if the TIE bit are 1.
The cycle of the PWM pulse can be changed by switching the count clock
pulse.
The count clock pulse can be selected from three clock pulses of the
prescaler and the clock pulse of the internal timer by the clock pulse select
bits P1 and P0 of the CNTR.
Peripherals
When COMR is 00
H
Counter value
00H
FFH 00H
PWM pulse output
When COMR is 80
H
Counter value
00H
80
H
FF
H 00H
80
H
PWM pulse output
When COMR is FF
H
Counter value
00H
FFH 00H
comparison match
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