HARDWARE CONFIGURATION
2– 35
(b) Pulse-width measurement function
a. Measurement start
Writing 1 at the EN bit (bit 7) and FC bit (bit 7) causes the counter to
enter the operation-enabled state. In this condition, counting starts when
the edge of the measured pulse input is detected. At the pulse-width
measurement function, counting down is started from FFH.
b. Measurement end and measured value
When measurement is terminated, the measured value is transferred to
the buffer, and the measurement-end flag IR (bit 1) and buffer-full flag
BF (bit 0) are set. causing the counter to re-enter the operation-enabled
state. At this time, an interrupt request is output when the IE bit (bit 5)
is set to 1. When the previous measured value cannot be read after
continuous pulse-width measurement, it is held by continuing to set the
BF flag. The new measured value is discarded.
c. Long pulse
When the counter underflows during measurement, the UF bit (bit 2) is
set to 1 to continue counting. In this case, an interrupt request is also
output when the IE bit (bit 5) is set to 1.
d. Measurement stop
Measurement stops when 0 is written at the EN bit (bit 7).
e. Calculation of pulse width
The count value when measurement is terminated is transferred as the
measured value to the buffer. Therefore, the pulse width should be
calculated using the following equation.
Pulse width = [(256 – count value) + (Number of TO counts inverted
×
256)]
× one cycle width of count clock pulse
f. Others
The counter remains in the operation-enabled state even after the end
of measurement, so continuous pulse-width measurement is possible.
Measurement of a High pulse width is started from the changing edge
of the input pulse. If the EN bit is enabled (EN = 1) when the input pulse
is already High, counting is performed after the next rising edge.
Fig. 2.13 Measurement of High Pulse Width
Peripherals
Input pulse
EN signal
Count
Count stop