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参数资料
| 型号： | MB89PV950CF |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, 5 MHz, MICROCONTROLLER, CQFP64 |
| 封装： | 0.80 MM PITCH, PIGGY BACK, MQFP-64 |
| 文件页数： | 48/110页 |
| 文件大小： | 619K |
| 代理商： | MB89PV950CF |
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HARDWARE CONFIGURATION
2– 27
Note that 1 is always read when the Read Modify Write instruction is
executed.
The meaning of each bit to be written is as follows:
Note: In the PWM operation mode, neither the read nor write values of
these bits have any meaning.
[Bit 1] OE: Output signal control bit
When bit 1 is 1, the port serves as the PWM timer output. In the timer
operation mode, a signal that is reversed each time the values of the counter
and the compare register match is output. In the PWM operation mode, a
PWM signal is output.
Even if the DDR of P41 is set for input (bit 1 of DDR4 is set to 1), when this
bit is 1, it serves as the counter/PWM output pin.
[Bit 0] TIE: Interrupt enable bit (Timer mode)
If bit 0 is set to 1, an interrupt occurs when the values of the counter and
the compare register match.
However, in the PWM operation mode, an interrupt does not occur
irrespective of the value of this bits.
0
1
Values of counter and COMR do not match.
Values of counter and COMR match.
Peripherals
0
1
Clears this bit
Does not change this bit nor affect other bits
0
1
General-purpose ports (P41)
Counter/PWM output pins (PWM)
0
1
Disables counter interrupt output
Enables counter interrupt output
(b) Compare register (COMR)
This register holds the value to be compared with the counter value in the
timer operation mode, and also clears the counter when the value agrees
with the counter value. In the PWM operation mode, the High pulse width
can be specified by this register value.
Address: 0013H
(Initial value)
XXXXXXXXB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(W)
CNTR
COMR
Address: 0012H
Address: 0013H
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