- 您现在的位置：买卖IC网 > PDF目录371012 > MC144144P (MOTOROLA INC) Digital Signal Processors 44-JLCC -55 to 125 PDF资料下载
参数资料
| 型号： | MC144144P |
| 厂商： | MOTOROLA INC |
| 元件分类： | 颜色信号转换 |
| 英文描述： | Digital Signal Processors 44-JLCC -55 to 125 |
| 中文描述： | COLOR SIGNAL DECODER, PDIP18 |
| 封装： | PLASTIC, DIP-18 |
| 文件页数： | 36/44页 |
| 文件大小： | 565K |
| 代理商： | MC144144P |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页当前第36页第37页第38页第39页第40页第41页第42页第43页第44页
MC144144
36
MOTOROLA
During data recovery time (TV lines 21 – 42), the com-
mand processor, in conjunction with the data recovery cir-
cuits, recovers the XDS data and the data for the selected
data channel. Data is sent to the RAM for storage and dis-
play and/or to the serial port, as appropriate. Where neces-
sary, the command processor converts the input data to the
appropriate form.
OUTPUT LOGIC
The output logic circuits operate together to generate the
output color signals RED, GREEN, and BLUE and the Box
signal. When MONOchrome mode is selected all three color
outputs will carry the luminance information. These outputs
are positive output logic signals.
The character ROM contains the dot pattern for all the
characters. The output logic provides the hardware under-
line, graphics characters, and the italics slant generator cir-
cuits. The smooth scroll display is achieved by the smooth
scroll counter logic controlling the addressing of the charac-
ter ROM.
DECODER CONTROL CIRCUIT
The decoder control circuit block is the user’s communica-
tions port. It converts the information provided to the control
port into the internal control signals required to establish the
operating mode of the decoder. This port can be operated in
one of two serial modes. The SMS pin is used to establish
the serial control mode to be used.
In the two–wire (I2C) control mode, the MC144144 will re-
spond to its slave address for both the read and write condi-
tions. If the read bit is low (indicating a WRITE sequence)
then the MC144144 will respond with an acknowledge. The
master should then send an address byte followed by a data
byte. If the read bit is high (indicating a READ sequence)
then the MC144144 will respond with an acknowledge fol-
lowed by a status byte then a data byte. Read data will only
be available through indirect addressing. Write addressing
will have both indirect and direct modes. The busy bit in the
status byte will indicate if the write operation has been com-
pleted or if read data is available.
The SPI mode is a three–wire bus with the MC144144 per-
forming as the slave device. Communications is synchro-
nized by the SCK signal generated by the master. Typically,
the serial data output is transmitted on the falling edge of
SCK and the received data is captured on the rising edge of
SCK. All data is exchanged as eight–bit bytes.
VOLTAGE/CURRENT REFERENCE
The voltage/current reference circuit uses an externally
connected resistor to establish the reference levels that are
used throughout the IC. The use of an external resistor pro-
vides improved internal precision at low additional cost.
PIN DESCRIPTIONS
INPUTS
Video (Pin 7)
Composite NTSC video input, 1.0 Vp–p (nom), band lim-
ited to 600 kHz. Circuit will operate with signal variation be-
tween 0.7 – 1.4 Vp–p. The polarity is sync tips negative. This
signal pin should be ac coupled through a 0.1
μ
F capacitor
and driven by a source impedance of 470
or less.
HIN (Pin 5)
Horizontal sync input at CMOS levels. When the part is
used in the VIDEO LOCK mode, this signal pulls the on–chip
VCO within the proper range. The circuit uses the frequency
of this signal which must be within
±
3% of Fh but can be of
either polarity. When used in the H LOCK mode the VCO
phase locks to the rising edge of this signal. The HPOL bit of
the H position register can be set to operate with either polar-
ity of input signal. This is usually the H flyback signal. The
timing difference between HIN rising edge and the leading
edge of composite sync (of VIDEO input) is one of the factors
which will affect the horizontal position of the display. Any
shift resulting from the timing of this signal can be compen-
sated for with the horizontal timing value in H position regis-
ter.
SMS (Pin 6)
Mode select pin for the serial control port. When this input
is at a CMOS HIGH state (1) the serial control port will oper-
ate in the SPI mode. When the input is LOW (0), the serial
control port will operate in the I2C slave mode. In the I2C
mode, the SEN pin must be tied HIGH (see
Reset Operation
discussion below).
SEN (Pin 4)
Enable signal for the SPI mode operation of the serial con-
trol port. When this pin is LOW (0), the SPI port is disabled
and the SDO pin is in the high–impedance state. Transitions
on the SCK and SDA pins are ignored. SPI mode operation
is enabled when this pin is HIGH (1).
SCK (Pin 15)
Input pin for serial clock signal from the master control de-
vice. In I2C mode operation the clock rate is expected to be
within I2C limits. In SPI mode, the maximum clock frequency
is 10 MHz.
RESET OPERATION
When the SMS and SEN pins are both in the LOW (0)
state, the part will be in the RESET state. Therefore, in the
I2C mode the SEN pin can be used as an NRESET input.
When SPI mode is used, if three–wire operation is desired,
both SMS and SEN can be tied together and used as the
NRESET input. In either mode, NRESET must be held LOW
(0) for at least 100 ns. Refer to
XDS Data Recovery
for fur-
ther details.
INPUT–OUTPUT
VIN/INTRO (Pin 13)
EXT VLK Mode:
In this mode of operation the internal ver-
tical sync circuits will lock to the VIN input signal applied at
this pin. The part will lock to the rising or falling edge of the
signal in accordance with the setting of the V polarity com-
mand. The default is rising edge. The VIN pulse must be at
least 2 lines wide.
INTRO Mode:
When configured for internal vertical syn-
chronization, this pin will be an output pin providing an inter-
rupt signal to the master control device in accordance with
the settings in the interrupt mask register.
相关PDF资料 |
PDF描述 |
|---|---|
| MC14415DW | Digital Signal Processors 40-CDIP SB -55 to 125 |
| MC14415FL | Quad Precision Timer/Driver |
| MC14415FP | Quad Precision Timer/Driver |
| MC14415VL | Digital Signal Processors 68-CPGA -55 to 125 |
| MC14415VP | Digital Signal Processors 68-LCCC -55 to 125 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MC14415FP | 制造商:Motorola Inc 功能描述: |
| MC14416P | 制造商:Motorola Inc 功能描述: 制造商:Motorola Inc 功能描述:TIME-SLOT ASSIGNER, 22 Pin, Plastic, DIP |
| MC14419P | 制造商:Motorola Inc 功能描述:ENCODER, 16 Pin, Plastic, DIP |
| MC14433P | 制造商:Motorola Inc 功能描述: |
| MC1443G | 制造商:Motorola Inc 功能描述: |
发布紧急采购，3分钟左右您将得到回复。